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參數(shù)資料
| 型號： | 240VA |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable 3.3V Generic Digital CrosspointTM |
| 中文描述： | 在系統(tǒng)可編程3.3V的通用數(shù)字CrosspointTM |
| 文件頁數(shù)： | 16/25頁 |
| 文件大?。?/td> | 324K |
| 代理商： | 240VA |
16
Specifications
ispGDX240VA
BUS_D.m0 = BUS_A;
BUS_D.m1 = BUS_B;
BUS_D.m2 = BUS_C;
BUS_D.m3 = VCC;
// Default all
// outputs to VCC
The GDF File
The GDF file is a simple text description of the design
function, device and pin parameters. The file has four
parts: device selection, set and constant statements, a
pin section and a connection section. A sample file looks
like this:
// 32-Bit Data 3 to 1 Mux
DESIGN
datamux;
PART ispGDX160V-7Q208;
PARAM SECURITY ON;
PARAM OPENDRAIN ON;
// USE OPEN DRAIN
// OPTION
// USE BUS HOLD
// LATCH OPTION
PARAM PULL HOLD;
SET
SET
SET
SET
BUS_A
BUS_B
BUS_C
BUS_D
[dataA31..dataA0];
[dataB31..dataB0];
[dataC31..dataC0];
[dataD31..dataD0];
INPUT
INPUT
INPUT
OUTPUT BUS_D
BUS_A
BUS_B
BUS_C
{A31..A0};
{B31..B0};
{C31..C0};
{D31..D0};
INPUT [oe]
INPUT [clk] {B36};
{B37};
INPUT [sel1]
INPUT [sel0]
{B38};
{B39};
BEGIN
BUS_D.s1 = sel1;
BUS_D.s0 = sel0;
BUS_D.oe = oe;
BUS_D.clk = clk;
END
This example shows a simple, but complete, 32-bit 3:1
MUX design. Once completed, the compiler takes over.
Powerful Syntax
Lattice
’
s ispGDX Design System uses simple, but power-
ful, syntax to easily define a design. The !(bang) operator
controls pin polarity and can be used in both the pin and
connection sections of the design definition. Dot exten-
sions define data inputs, select controls for the 4:1
multiplexor, and control inputs of sequential elements
and tri-state buffers. Dot extensions are .M# (MUX Input),
.S# (MUX Select), and control functions, such as .CLK,
.EN, .OE and .A (shown in adjacent table). Pin Attributes
are assigned in the pin section of the GDF as well.
SLOWSLEW selects the slow slew rate for an output
buffer. The Pull parameter can be used to select the
internal pull-up or bus hold latch. OPEN drain can be
used to select open drain operation. The COMB attribute
distinguishes the structure for bidirectional pins. If COMB
is used, the input register, or latch, of an output buffer will
be applied to bidirectional pins.
Please consult the ispGDX Development System Manual
for full details.
Type
Dot Ext.
.M0
.M1
.M2
Description
MUX
Input
MUX
Selection
Control
MUX
Output
MUXA Data input to 4:1 MUX
MUXB Data input to 4:1 MUX
MUXC Data Input to 4:1 MUX
MUX0 Selection input to 4:1 MUX
MUX1 Selection input to 4:1 MUX
Clock for a register
Latch enable for a latch signal
Output enable for 3-state output
or bidirectional signal
.M3
.S0
.S1
.CLK
.EN
.OE
MUXD Data input to 4:1 MUX
.CE
Clock enable for register clock
.A
Adjacent MUX output of an I/O cell
ispGDXV Dot Ext
ispGDX GDF File Dot Extensions
ispGDX Development System (Continued)
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