參數(shù)資料
型號： 2192VE
廠商： Lattice Semiconductor Corporation
英文描述： 3.3V In-System Programmable SuperFAST⑩ High Density PLD
中文描述： 3.3在系統(tǒng)可編程超快⑩高密度可編程邏輯器件
文件頁數(shù)： 9/15頁
文件大?。?/td> 144K
代理商： 2192VE
Specifications
ispLSI 2192VE
9
ispLSI 2192VE Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
#24
20 PT
XOR Delays
Control
PTs
#33, 34,
35
I/O Pin
(Input)
Y0,1,2
GRP
#22
GLB Reg Bypass
#28
ORP Bypass
#37
D
Q
RST
RE
OE
CK
I/O Delay
#20
I/O Cell
ORP
GLB
GRP
I/O Cell
#25, 26, 27
#43, 44
#36
Reset
Ded. In
#21
#29, 30,
31, 32
#38,
39
GOE 0
#42
#40, 41
0491/2032
Comb 4 PT Bypass #23
#45
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
=
(0.3 + 0.2 + 3.2) + (0.7) - (0.3 + 0.2 + 0.8)
t
h
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.3 + 0.2 + 3.2) + (1.8) - (0.3 + 0.2 + 3.2)
2.9ns
t
su
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
=
=
=
=
=
=
=
=
t
co
Note: Calculations are based upon timing specifications for the ispLSI 2192VE-225L.
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.3 + 0.2 + 3.2) + (0.3) + (0.9 + 1.6)
Table 2-0042A/2192VE v0.1
3.6ns
8.4ns
相關(guān)PDF資料
PDF描述
21934 CAPACITIVE SENSOR
21A Low-Frequency Dual EconOscillator
21B Low-Frequency Dual EconOscillator
21C Low-Frequency Dual EconOscillator
21D Low-Frequency Dual EconOscillator
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