參數(shù)資料
型號(hào)： 2192VE
廠商： Lattice Semiconductor Corporation
英文描述： 3.3V In-System Programmable SuperFAST⑩ High Density PLD
中文描述： 3.3在系統(tǒng)可編程超快⑩高密度可編程邏輯器件
文件頁(yè)數(shù)： 5/15頁(yè)
文件大?。?/td> 144K
代理商： 2192VE
Specifications
ispLSI 2192VE
5
External Timing Parameters
Over Recommended Operating Conditions
3.5
–
–
–
–
UE
–
–
NN
–
10.0
10.0
5.0
5.0
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
UNITS
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030A/2192VE
1
3
2
1
( )
DESCRIPTION
#
PARAMETER
A
A
A
1
2
3
Data Propagation Delay, 4PT Bypass, ORP Bypass
Data Propagation Delay
Clock Frequency with Internal Feedback
ns
ns
MHz
–
–
–
A
–
4
5
6
7
8
Clock Frequency with External Feedback
Clock Frequency, Max. Toggle
GLB Reg. Setup Time before Clock, 4 PT Bypass
GLB Reg. Clock to Output Delay, ORP Bypass
GLB Reg. Hold Time after Clock, 4 PT Bypass
MHz
MHz
ns
ns
ns
–
A
–
A
–
B
C
B
C
9
GLB Reg. Setup Time before Clock
GLB Reg. Clock to Output Delay
GLB Reg. Hold Time after Clock
Ext. Reset Pin to Output Delay
Ext. Reset Pulse Duration
Input to Output Enable
Input to Output Disable
Global OE Output Enable
Global OE Output Disable
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
11
12
13
14
15
16
17
–
–
18
19
External Synchronous Clock Pulse Duration, High
External Synchronous Clock Pulse Duration, Low
ns
ns
-180
MIN. MAX.
–
–
180
5.0
7.5
–
–
–
–
–
4.5
–
0.0
–
4.0
–
–
2.5
2.5
–
–
125
200
3.5
3.5
–
–
4.5
–
7.0
-225
MIN. MAX.
–
–
225
4.0
6.2
–
–
–
–
–
0.0
3.5
–
0.0
–
2.0
2.0
–
–
150
250
2.5
3.2
–
–
3.7
–
6.0
–
6.0
6.0
4.5
4.5
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