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| 型號(hào)： | 21582 |
| 英文描述： | Gigabit Ethernet Physical Layer GigaPHY-SD Device Design Considerations? 49.2KB (PDF) |
| 中文描述： | 千兆以太網(wǎng)物理層GigaPHY - SD設(shè)備設(shè)計(jì)考慮？ 49.2KB（PDF格式） |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 49K |
| 代理商： | 21582 |
2
Design Considerations for the Am79761 Gigabit Ethernet Physical Layer GigaPHY-SD Device
Figure 1.
Common REFCLK versus Separate REFCLK
HIGH SPEED SIGNAL TERMINATION
The differential high speed outputs of the transmitter
(TX+ and TX-) are PECL outputs, which require unique
termination to ensure proper operation and optimize
signal quality. Since these signals are clocked at 1.25
GHz and transmit 8B/10B encoded data, they carry
digital signals between 125 MHz and 625 MHz. Careful
design and layout of the terminations and traces are re-
quired to maximize transmission distance and mini-
mize signal degradation. The multiple media choices
further complicate the use of these circuits. For the pur-
poses of this discussion, four applications will be de-
scribed for both the transmitter outputs (TX
receiver inputs (RX
±
):
±
) and the
I
Single-Ended/Differential Coaxial Cable using 50-
SMA connectors for test equipment connectivity.
Single Ended, 75-
Coaxial Cable using BNC/TNC
connectors for Fibre Channel and Gigabit Ethernet
compatibility
Differential, 150-
Duplex Twinax Cable using DB-
9 connectors for Fibre Channel and Gigabit Ether-
net compatibility.
Fiber Optic Module interface at 50-
I
I
I
.
The transmitter outputs (TX
are capable of sourcing current but not sinking it.
Therefore a pull-down resistor (traditionally to VDD -
2.0 V) is required to drive a LOW on the output when
the output FET is turned off. The resistance of this pull-
down is determined by the parametrics of the part and
impedance of the signal trace. Since VDD -2.0 V is usu-
ally not present in the system, the output should be ter-
minated to ground (VSS) for convenience. Also, PECL
outputs do not conform to ECL input levels, therefore,
all high speed I/O should be AC-coupled to eliminate
mismatches in signal levels.
±
) are PECL outputs which
The receiver inputs (RX
which include resistor dividers to set the bias point of
the input (usually at VDD/2). Normally, the user sup-
plies resistors to terminate the transmission line and
minimize reflections. An AC-coupling capacitor is pro-
vided to isolate the PECL input from the transmission
line to let the input buffer set its own DC bias point.
±
) are differential PECL inputs
Lastly, a mechanism may be added to provide a DC off-
set, so that if the input is open, the input buffer will not
oscillate. The following sections describe the designs
of various termination schemes which provide some,
but certainly not all, of the options open to the user.
Single-Ended, 50-
Termination
This application is ideal for connecting to test equipment
such as oscilloscopes and BERTs but does not conform
to the Gigabit Ethernet specification. On the transmitter
outputs, a 182-
pull-down resistor is located near the
pin of the device in order to pull the signal to a LOW level
when the output FET is turned off. The value of 182
used with 50-
impedance traces/cables. An AC-cou-
pling capacitor (usually 0.01
eliminate the DC component of the output signal allow-
ing general-purpose connectivity.
is
μ
F) is added in series to
On the receiver inputs, a 51.1-
tor is provided to match the impedance of the trace and
coaxial cable to reduce reflections and optimize signal
quality. An AC-coupling capacitor is added in series to
allow the input buffer to establish the optimal DC-level
provided by its internal resistor dividers. This will re-
store signal levels to meet the input requirements of the
high speed buffer. The unused receiver input is AC-
coupled to ground to reduce noise susceptibility, but
keeps the input at the internal bias point. The 50-
axial cable would normally be connected using SMA
connectors for ease of use with test equipment. The
shells of the SMA connectors are grounded. The typical
circuit for this application is shown in Figure 2.
line termination resis-
co-
Output
Latch
>
125 MHz
±100 ppm
Less Jitter
Worse Setup/Hold Time
REFCLK
>
Input
Register
Encoder/Decoder
GigaPHY-SD
Output
Latch
>
More Jitter
Better Setup/Hold Time
REFCLK
>
Input
Register
Encoder/Decoder
GigaPHY-SD
Oscillator
Oscillator
125 MHz
±100 ppm
21582B-1
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