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參數(shù)資料
| 型號： | 21531G |
| 英文描述： | Programmable 8 bit Silicon Delay Line |
| 中文描述： | AMD的快閃記憶體快速參考指南- 2003年2月版 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 606K |
| 代理商： | 21531G |
6
2.5 Volt-only Flash Memory
3.0 Volt-only Flash Memory
S
P
32 MBit
Am29PDS322D
T, B
10 (40),
12 (45)
6
WM (48)
I
1.8–2.2
NA
2 M x 16
SecSi Sector, WP#/ACC, CFI. Bank split 4/28Mb.
Banks 1–2 (Kw): [(8)4,(7)32] [(56)32]
S
16 Mbit
Am29DS163D
T, B
100, 120
WA (48)
I, E
1.8–2.2
NA
2 M x 8,
1 M x 16
SecSi Sector, WP#/ACC, CFI. Bank split 4/12 Mb.
Banks 1–2 (KB): [(8)8,(7)64] [(24)64]
32 Mbit
Am29DS323D
T, B
110, 120
E (48),
WM (48)
I
1.8–2.2
NA
4 M x 8,
2 M x 16
SecSi Sector, WP#/ACC, CFI. Bank split 8/24 Mb.
Banks 1–2 (KB): [(8)8,(15)64] [(48)64]
32 Mbit
Am29DS320G
T, B
70, 90, 120
E (48),
WM (48)
I, E
1.8–2.2
NA
4 M x 8,
2 M x 16
SecSi Sector, WP#/ACC, CFI. Four banks, split 4/12/12/4 Mb. Sector
sizes (KB): [(8)8,(7)64] [(24)64] [(24)64] [(8)64]
32 Mbit
Am29DS322G,
Am29DS323G,
Am29DS324G
T, B
70, 90, 120
E (48),
WM (48)
I
1.8–2.2
NA
4 M x 8,
2 M x 16
SecSi Sector, WP#/ACC, CFI. Four banks, split 4/12/12/4 Mb. Sector
sizes (KB): [(8)8,(7)64] [(24)64] [(24)64] [(8)64]
C
8 Mbit
Am29SL400C
T, B
100R
E (48), WB (48)
C, I
1.75–2.2
NA
512 K x 8,
256 K x 16
Sector sizes (KB): 16,8,8,32,(7)64
110, 120, 150
1.65–2.2
8 Mbit
Am29SL800D
T, B
100, 120, 150
E (48), F (48),
WC (48)
C, I
1.65–2.2
NA
1 M x 8,
512 K x 16
Sector sizes (KB): 16,8,8,32,(15)64
16 Mbit
Am29SL160C
T, B
90, 100,
120, 150
E (48), WC (48)
C, I, E
1.8–2.2
NA
2 M x 8,
1 M x 16
WP#/ACC, CFI. Sector sizes (KB): (8)8,(31)64
Architecture
2
Density
Ordering Part Number
1
Voltage
Supply
Byte/Word
Count x Bus
Width
Additional Features,
Sector Size/Count
5
Device Number
Sector
3
Access Times (ns),
(Clock Speed)
Package
(Pin/Ball Count)
4
Temp.
Range
Sim. R/W +
Burst Mode
16 Mbit
Am29BDD160G
T, B
7
54D, 65D (66 MHz),
64C (56 MHz),
65A (40 MHz)
8
K (80), PB (80)
I, E
2.3–2.75 V
1 M x 16,
512 K x 32
SecSi Sector, VersatileIO, WP#, ACC, CFI, Advanced
Sector Protection, Bank Split 4/12 Mb or 12/4 Mb.
7
A
2
Density
Ordering Part Number
1
Voltage Range
Byte/Word
Count x Bus
Width
Additional Features,
Sector Size/Count
5
Device Number
Sector
3
Access Times (ns)
Package
(Pin/Ball Count)
4
Temp.
Range
V
CC
2.7–3.1
V
IO
S
64 Mbit
Am29PDL640G
T B
9
73 (25), 83 (30)
10
WH (63), WS (80)
I
2.7–3.6
4 M x 16
Advanced Sector Protection, WP#/ACC, CFI,
VersatileIO. Bank split 16/48/48/16Mb. Banks 1–4
(Kw): [(8)4,(15)32] [(48)32] [(48)32] [(15)32,(8)4]
98 (30)
10
2.7–3.1
1.65–1.95
128 Mbit
Am29PDL127H
T, B
9
53 (20),
63, 83 (30)
10
VK (80), PC (64)
I
2.7–3.6
2.7–3.6
8 M x 16
Two PDL640H devices in a single package with
single CE# input. Advanced Sector Protection,
WP#/ACC, CFI. Bank split 16/48/48/16Mb. Banks
1–4 (Kw): [(8)4,(31)32] [(96)32] [(96)32] [(31)32,(8)4]
68, 88 (30)
10
2.7–3.6
1.65–1.95
128 Mbit
Am29PDL128G
T B
9
70R (25)
10
PE (80)
I
3.0–3.6
NA
8 M x 16,
4 M x 32
Advanced Sector Protection, WP#/ACC, CFI. Bank
split 16/48/48/16Mb. Banks 1–4 (Kw): [(8)4,(31)32]
[(96)32] [(96)32] [(31)32,(8)4]
70 (25),
80 (30)
10
I, E
2.7–3.6
NA
128 Mbit
Am29PDL129H
T, B
9
53 (20),
63, 83 (30)
10
VK (80)
I
2.7–3.6
2.7–3.6
8 M x 16
Two PDL640H devices in a single package with dual
CE# inputs. Advanced Sector Protection, WP#/ACC,
CFI. Bank split 16/48/48/16Mb. Banks 1–4 (Kw):
[(8)4,(31)32] [(96)32] [(96)32] [(31)32,(8)4]
68, 88 (30)
10
2.7–3.6
1.65–1.95
1.8 Volt-only Flash Memory (Continued)
A
2
Density
Ordering Part Number
1
Voltage Range
Byte/Word
Count x Bus
Width
Additional Features,
Sector Size/Count
5
Device Number
Sector
3
Access Times
(ns)
Package
(Pin/Ball
Count)
4
Temp.
Range
V
CC
V
IO
Notes:
1.
2.
3.
4.
5.
Contact AMD or an AMD representative for availability. See Ordering Part Number Designators table and individual data sheets for details. Products listed in italics are not yet introduced.
Sim R/W = Simultaneous Read/Write feature: Read from one bank while writing to any other bank.
Sector architecture: U = Uniform, T = Top boot, B = Bottom boot.
Pin/ball count provided in parenthesis is for information only, and is not included in the actual ordering part number.
Features:
WP# = Write protect input. ACC = Programming acceleration input. SecSi Sector = Secured Silicon (unique/random ID). CFI = Common Flash Interface.
Bank & Sector Size/Count:
Bank contents are given
in square brackets. Sector counts are given in parentheses. Kw = kilowords, KB = kilobytes, Mb = megabits.
PDS322D asynchronous access time is given first (10 = 100 ns, 12 = 120 ns), followed by the page mode access time in parentheses.
BDD160G: T = 4/12 Mbit bank split, Banks 1/2 (Kw): [(8)4,(7)32] [(8)4,(23)32]; B = 12/4Mbit bank split, Banks 1/2 (Kw): [(8)4,(23)32] [(8)4,(7)32]
BDD160G access times are for maximum initial burst read or asynchronous read operations.
This product has the Flexible Bank feature, which allows the device to be configured as a top or bottom boot device. Sector designators (T, B) are thus not included in part number.
The asynchronous access time is given first, followed by the burst (or page) mode access time in parentheses. For PDL640G/127H/129H asynchronous access times: 53 = 55 ns; 63, 68 = 65 ns; 73 = 70 ns;
83, 88= 80 ns; 98 = 90 ns. speed designators ending in “3” indicate a 3 V (2.7–3.1 V) V
IO
range, while those ending in “8” indicate a 1.8 V (1.65–1.95 V) V
IO
range.
6.
7.
8.
9.
10.
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