參數(shù)資料
型號: 2128E
廠商: Lattice Semiconductor Corporation
英文描述: In-System Programmable SuperFAST⑩ High Density PLD
中文描述: 在系統(tǒng)可編程超快⑩高密度可編程邏輯器件
文件頁數(shù): 7/11頁
文件大?。?/td> 142K
代理商: 2128E
Specifications
ispLSI 2128E
7
ispLSI 2128E Timing Model
Note: Calculations are based upon timing specifications for the ispLSI 2128E-180L.
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
=
=
=
=
(0.5 + 0.6 + 3.9) + (0.7) - (0.5 + 0.6 + 1.0)
t
h
Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.5 + 0.6 + 4.0) + (3.3) - (0.5 + 0.6 + 3.9)
3.4
t
su
Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
=
=
=
=
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 0.6)
Table 2-0042/2128E
7.9
3.6
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
#24
20 PT
XOR Delays
Control
PTs
#33 - 35
I/O Pin
(Input)
Y0,1,2
GRP
#22
GLB Reg Bypass
#28
ORP Bypass
#37
D
Q
RST
RE
OE
CK
I/O Delay
#20
I/O Cell
ORP
GLB
GRP
I/O Cell
#25 - 27
#43, 44
#36
Reset
Ded. In
#21
#29 - 32
GOE0, 1
#42
#40, 41
0491/2128E
Comb 4 PT Bypass #23
#45
#38,
#39
相關(guān)PDF資料
PDF描述
2128VE 3.3V In-System Programmable SuperFAST⑩ High Density PLD
2128VL 2.5V In-System Programmable SuperFAST⑩ High Density PLD
21303 MARKER DETERGENT RMVBL BLUE
21304 MARKER DETERGENT RMVBL BLACK
21306 MARKER DETERGENT RMVBL RED
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