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參數(shù)資料
| 型號(hào)： | 2128E |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | In-System Programmable SuperFAST⑩ High Density PLD |
| 中文描述： | 在系統(tǒng)可編程超快⑩高密度可編程邏輯器件 |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 142K |
| 代理商： | 2128E |
Specifications
ispLSI 2128E
5
t
pd1
t
pd2
f
max
f
max (Ext.)
f
max (Tog.)
t
su1
t
co1
t
h1
t
su2
t
co2
t
h2
t
r1
t
rw1
t
ptoeen
t
ptoedis
t
goeen
t
goedis
t
wh
t
wl
UNITS
-180
MIN.
–
–
180
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/2128E
1
1
( )
-135
MIN.
–
–
135
MAX.
5.0
7.5
MAX.
7.5
10.0
DESCRIPTION
#
2
4
PARAMETER
A
A
A
1
2
3
Data Prop Delay, 4PT Bypass, ORP Bypass
Data Prop Delay
Clk Freq with Internal Feedback
3
ns
ns
MHz
–
–
–
–
–
A
–
4
5
6
7
8
Clk Freq with External Feedback
Clk Frequency, Max. Toggle
GLB Reg Setup Time before Clk, 4 PT Bypass
GLB Reg Clk to Output Delay, ORP Bypass
GLB Reg Hold Time after Clk, 4 PT Bypass
–
–
–
–
–
–
MHz
MHz
ns
ns
ns
–
–
0.0
–
–
–
–
A
–
B
C
B
C
9
GLB Reg Setup Time before Clk
10 GLB Reg Clk to Output Delay
11 GLB Reg Hold Time after Clk
12 External Reset Pin to Output Delay
13 External Reset Pulse Duration
14 Input to Output Enable
15 Input to Output Disable
16 Global OE Output Enable
17 Global OE Output Disable
5.0
–
0.0
–
4.0
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
18 External Synch Clk Pulse Duration, High
19 External Synch Clk Pulse Duration, Low
2.5
2.5
–
–
–
–
ns
ns
125
200
4.0
3.0
–
–
3.5
–
7.0
–
10.0
10.0
5.0
5.0
100
143
5.0
0.0
6.0
0.0
5.0
3.5
3.5
4.0
4.5
10.0
12.0
12.0
7.0
7.0
-100
MIN. MAX.
–
–
100
10.0
13.0
–
–
–
–
–
0.0
8.0
–
0.0
–
6.5
–
–
–
–
5.0
5.0
–
–
77.0
100
6.5
5.0
–
–
6.0
–
13.5
–
15.0
15.0
9.0
9.0
External Timing Parameters
Over Recommended Operating Conditions
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