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參數(shù)資料
| 型號： | 21176 |
| 英文描述： | Designing 100BASE-TX? 86.8KB (PDF) System with the QFEX Family ? |
| 中文描述： | 設(shè)計100BASE - TX的？ 86.8KB（PDF格式）系統(tǒng)？與QFEX家庭 |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 86K |
| 代理商： | 21176 |
4
Designing 100BASE-TX Systems with the QFEX Family
MII and Repeater Interface
There are two ways to interface a repeater or MAC to a
PHY device. The standard way is using the MII inter-
face, described in the 100BASE-X standard. The other
method is using the standard 5-bit symbol interface,
which will be described shortly.
The MII interface provides the basic signals needed to
perform the necessary handshaking for the repeater
and PHY to link and transfer data. Eighteen signals
control the receive, transmit, and management pro-
cesses. The 100BASE-X Reconciliation layer then
converts these signals into primitive directives (data
request and indication, carrier indication, and signal
indication) that inform the PHY of what’s happening
across the interface.
The QFEXr device offers a Shared MII port. In repeat-
ers, data is received on one port and is broadcast
through the other ports. Pin count is greatly reduced,
as seen in the 100-pin QFEXr package.
With this Shared MII, connecting four PHY ports to
the repeater is much simpler than connecting four
separate MII ports. The connection to the repeater
through the MII port requires no glue logic, except for
passives required for AC termination and reduction of
high-speed effects.
Figure 4.
QFEXr Connection to Repeater (using Shared MII Interface)
As seen in Figure 4, the connection to the repeater
through the MII port requires no glue logic, except for
passives required for AC termination and reduction of
high-speed effects.
For transmitting, the TXD[3:0] bus is connected directly
to the repeater, as are the transmit enable signals,
TX_EN[3:0]. The QFEXr device provides the option for
using TX_CLK or system CLK as the internal timing ref-
erence. So, TX_CLK may or may not be used. TX_ER
from the repeater is tied to all four TX_ER signals on
the QFEXr device to inform all ports of any possible
transmission error.
When receiving, the RXD[3:0] bus is connected directly
to the repeater, and the ENRCV[3:0] (port receive
C
C
T
T
T
R
T
R
R
R
M
M
100 Mbps
Repeater
4-port
Shared
MII Signals
100
BASE-X
UTP
PMD
Medium
100 BASE-TX
Repeater
MII
QFEXr
Shared MII
Circuitry
PCS2
PCS3
PMA0
PCS1
PMA3
PMA2
PMA1
PCS0
QFEXr
4-port
Non-shared
MII Signals
21176B-4
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