12
Designing 100BASE-TX Systems with the QFEX Family
Plane partitioning methods can vary widely from an
ultra-conservative design (i.e., separate power and
ground planes per port and PHY device, with DVDD fil-
tering using ferrite beads) to the other extreme (i.e.,
large power and ground planes, with limited or no filter-
ing). Because of the different components (noise
sources, IC’s, etc.) acting at the same time in the sys-
tem, it is hard to pinpoint an exact design and layout
method that will work in every case. Even the choice of
components (transformers, etc.) can have an impact on
the system passing FCC guidelines.
The recommendations listed here focus on the PHY
and leaves it up to the designer to tackle the compo-
nents and issues beyond the MII interface. Likewise,
MLT-3 layout is dependent on the components and the
MLT-3 vendor recommendations. Consult the MLT-3
transceiver vendor for information.
The QFEXr device is a four port device with MII inter-
faces and MLT-3 or PECL interfaces. The MII interface
lies in the digital portion of the board and, therefore,
should be overlaid by a digital power and ground plane.
PECL ports can be overlaid by digital or PECL planes,
but PECL planes are recommended. Notice that the
QFEXr device should have a separate PDX plane to
ensure a clean power signal is sent to the on-board
PLL. Thus, layout for the QFEXr device should consider
these three planes, as outlined by the following options:
Option 1
Power plane layout:
— One PECL plane for each port, separated from
main power by ferrite beads
— One PDX plane also separated by a ferrite bead
— Remainder of the device to reside in the CMOS
VCC power plane with CMOS
Ground plane layout:
— All ports and the device reside in CMOS VDD
ground plane
Option 2
Power plane layout same as option 1
Ground plane layout:
— All ports reside in a separate PECL ground
plane (no ferrite beads), separated from main
— Ground except in one area (the “neck”)
— Remainder of the device to reside in CMOS VDD
ground plane
Option 3
Power plane layout same as option 1
Ground plane layout:
— One PECL plane for each port, separated from
main ground except in one area (the “neck”)
I
I
I
I
I
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— Remainder of the device to reside in CMOS VDD
ground plane
An alternate power plane layout that seems to work is
to provide one PECL plane for all ports and still main-
tain the separate plane for the PDX. A multiport design
can benefit from this simplified layout, where each
QFEXr device has its own PECL and PDX planes.
However, it remains to be seen how the device can tol-
erate the added noise from inter-port crosstalk, as well
as how stable the design would be to be able to pass
FCC tests. This alternate scheme can be combined
with any of the ground plane options listed above.
Figure 9 illustrates an example layout of power planes
that aims to minimize potential noise sources which
may detract from good EMI performance. It is impor-
tant to separate the sensitive PECL from the noisy
CMOS levels, and ferrite beads provide good filtering
for this purpose. Having separate PECL planes also
minimizes crosstalk from adjacent ports. Thus, four
ferrite beads are recommended to separate PECL
planes from the digital CMOS VCC plane. Additionally,
to insure a clean power supply to the PDX, an addi-
tional ferrite bead is placed on the DVDD_D pin or on
the plane underlying that pin to filter out noise from
the connecting CMOS VCC plane. So, each QFEXr
device can have up to five ferrite beads for power
plane isolation. In multiport systems and using the al-
ternate power plane layout option, this can be relaxed
to two ferrite beads, one for the PECL plane and one
for the PDX plane of the QFEXr device.
Layout of the ground plane will greatly affect the de-
sign, as foreseen by the above three options. Ground
plane layout, as well as power plane layout, should take
into consideration the signal-return path for the AC cur-
rent generated every time a signal switches. Once the
signal has returned, the current loop has been com-
pleted. AC return signals have an entire plane in which
to choose a path, but they take the path of least imped-
ance (inductance and capacitance) to the current and
not necessarily in a straight line. If there are physical
breaks in the return signal plane, the signal has to cir-
cumvent the break, thereby, increasing inductance and
loop size.
The easiest ground plane layout as shown in the op-
tions would involve a common digital ground plane,
connecting with the remainder of the system beyond
the MII interface. However, because of the CMOS lev-
els, a fair amount of noise can affect the PECL outputs.
In light of this, a separate PECL ground plane would
serve to separate most of the interference. The PECL
ground plane and system ground plane would be two
separate islands with a cut at the joining of both planes,
placed appropriately to aid in the return signal path.
This cut (or “neck”) is the only “entrance” for ground into
either plane, and a decoupling capacitor can be added
to moderate the frequency behavior. Ferrite beads are