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參數(shù)資料
| 型號(hào)： | 21050 |
| 英文描述： | 21050 - 21050 PCI-to-PCI Bridge Hardware Implementation Application Note |
| 中文描述： | 21050 - 21050 PCI至PCI橋的硬件實(shí)現(xiàn)應(yīng)用筆記 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 92K |
| 代理商： | 21050 |
21050 PCI-to-PCI Bridge Hardware Implementation
8
Application Note
3.3
Clock Implementation on the Motherboard
If the 21050 is implemented on a motherboard and the secondary bus is routed to one or more PCI
expansion card slots or to another 21050, you should not use the 21050 secondary clock outputs
s_clk_o<6:0>, unless the designer can guarantee that the output clocks will meet PCI duty cycle
specifications. This may be possible by controlling the skew of p_clk. Because an expansion card
could implement a 21050, never route secondary clock outputs to an expansion card slot.
If you cannot use secondary clock outputs due to the restrictions listed in this section, you can
substitute a low skew clock buffer that preserves duty cycle to generate secondary clocks. For
example:
Texas Instruments—CDC328A
National Semiconductor—CGS74B2525
IDC—1DT74FCT805CT
One of the secondary clock signals must be connected to the 21050 secondary clock input s_clk.
Plan the layout of clocks to minimize skew between the 21050 and other PCI devices.
If the 21050 secondary bus does not connect to any PCI option card slots or to the primary interface
of another 21050, then you can use the secondary clock outputs according to the guidelines given
in the following section.
3.4
Clock Implementation on an Option Card
If the 21050 is implemented on an option card, then you must use the secondary clock outputs for
devices connected to the secondary bus and for the 21050 secondary clock input s_clk, because
CLK signals coming from the card edge can be connected to only one load (in this case, the 21050
primary clock input p_clk). You cannot also use the CLK signal from the card edge to generate
secondary clocks externally.
Follow these guidelines when implementing secondary clock outputs:
Connect one s_clk_o<6:0> output to the 21050 s_clk input.
Route s_clk_o<6:0> to minimize skew, that is, use the same amount of etch for the
s_clk_o<6:0> outputs that are used as s_clk inputs as you use for the other s_clk_o<6:0>
signals. It is recommended that the amount of delay due to etch be limited to less than 2 ns (10
inches if etch has a delay of 200 ns/inch).
It is recommended that you use a series termination resistor of 20 Ohms to terminate the
s_clk_o<6:0> outputs to limit reflections on the clock lines. Locate these resistors as close as
possible to the 21050 s_clk_o<6:0> pins.
4.0
Secondary IDSEL Mapping
The
PCI Local Bus Specification
defines two formats for configuration transactions in hierarchical
systems:
Type 0 configuration transactions are used to configure devices on the same PCI bus.
Type 1 configuration transactions are used to configure devices that reside on a downstream
PCI bus.
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