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參數(shù)資料
| 型號： | 20V8 |
| 廠商： | Cypress Semiconductor Corp. |
| 元件分類： | PAL |
| 英文描述： | Flash Erasable, Reprogrammable CMOS PAL Device |
| 中文描述： | 閃光可擦除，可再編程的CMOS PAL制式設(shè)備 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 352K |
| 代理商： | 20V8 |
PALCE20V8
Document #: 38-03026 Rev. **
Page 2 of 14
Shaded area contains preliminary information.
Functional Description
(continued)
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a mac-
rocell can be used either as an internal output enable control
or as a data product term.
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are select-
able from either the input/output pin associated with the mac-
rocell, the input/output pin associated with an adjacent pin, or
from the macrocell register itself.
Power-Up Reset
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the associ-
ated output pin will be HIGH due to active-LOW outputs.
Electronic Signature
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can con-
tain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the in-
ternal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each prod-
uct term. The PTD fuses allow each product term to be individ-
ually disabled.
Input and I/O Pin Pull-Ups
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active
HIGH state (logical 1). All unused inputs and three-stated I/O
pins should be connected to another active input, V
CC
, or
Ground to improve noise immunity and reduce I
CC
.
Pin Configuration
PLCC/LCC
Top View
0
20V8
–
2
DIP/QSOP
Top View
25
24
23
22
21
20
19
5
6
7
8
9
10
11121314 1516 1718
4 3 2
2827 26
I
2
I
1
C
V
I
1
I
7
C
1
N
1
2
3
4
5
6
7
8
9
10
11
12
14
13
15
16
20
19
18
17
21
24
23
22
OE/I
11
I/O
7
I/O
6
I/O
5
I/O
4
I/O
0
I
12
I/O
2
I/O
1
I/O
3
V
CC
I
13
GND
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
CLK/I
0
20V8
–
3
I
10
I
3
I
4
I
5
I
6
I
7
I
8
NC
I/O
2
I/O
1
I/O
6
I/O
5
I/O
4
NC
I/O
3
1
I
9
I
G
N
1
O
1
I
0
I
Selection Guide
Generic Part Number
PALCE20V8
5
PALCE20V8
7
PALCE20V8
10
PALCE20V8
15
PALCE20V8
25
PALCE20V8L
15
PALCE20V8L
25
t
PD
ns
t
S
ns
t
CO
ns
I
CC
mA
Com
’
l/Ind
5
7.5
10
15
25
15
25
Mil
Com
’
l/Ind
3
7
10
12
15
12
15
Mil
Com
’
l/Ind
4
5
7
10
12
10
12
Mil
Com
’
l
115
115
115
90
90
55
55
Mil/Ind
10
15
25
15
25
10
12
20
12
20
10
12
20
12
20
130
130
130
65
65
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