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參數(shù)資料
| 型號： | 20747 |
| 英文描述： | Using a PCMCIA Card as a Boot ROM on an ?lanSC300 Microcontroller Design ?lanSC300/?lanSC310 ISA Bus Anomalies |
| 中文描述： | 以此為啟動ROM上？lanSC300微控制器設(shè)計？lanSC300 /？lanSC310 ISA總線異常一個PCMCIA卡 |
| 文件頁數(shù)： | 2/3頁 |
| 文件大小： | 38K |
| 代理商： | 20747 |
2
élanSC300 and élanSC310 Devices’ ISA Bus Anomalies
Summary:
If the system design demands a 16-bit ISA
device and fast 8-bit ROM accesses, the MEMCS16
and/or IOCS16 signal must become inactive less than
30 nsec after the end of the ISA cycle. This will not be
an issue if the system design does not use a 16-bit ISA
device, or if the system design does not implement fast
ROM cycles.
BALE
BALE is the ISA Address Latch Enable signal. It is used
by devices to latch in the LA23:17 address lines. These
LA address lines are not latched in the élanSC300 and
SC310 devices and so are not held active for the entire
ISA cycle. BALE and the LA23:17 signals are available
on the élanSC300 and SC310 microcontroller pins in
Maximum ISA mode. Since the SA23:0 address lines
are already latched in the élanSC300 and SC310 mi-
crocontrollers, devices that use them should not need
a BALE.
The BALE signal is asserted for each ISA cycle to allow
an ISA device to latch in the LA signals and use them
to determine if the cycle is for that device. The problem
encountered is that BALE does not get asserted for fast
ROM cycles (it is asserted for slow ROM cycles, so
these are not at issue). This is not a problem for the
ROM, but if an ISA device that uses BALE is accessed,
and the following access is a fast access to the ROM,
since the fast ROM access does not generate a BALE,
the ISA device may acknowledge the ROM cycle as its
own (the ISA device is using the latched address from
the previous cycle). This will result in either a conflict on
the data bus in the case of a Read, or in faulty data
being written to the ISA device in the case of a Write.
Summary:
It is not recommended to design a system
with ISA devices that need to use BALE if the design
will also implement fast ROM accesses. If it is neces-
sary to use an ISA device that needs BALE, the follow-
ing board and software changes can be done:
Externally qualify the ISA memory commands (MEMR
and MEMW) with the ROM chip selects (ROMCS and/
or DOSCS) that are running at a fast rate. Route the
new qualified memory commands to any ISA devices
that use BALE. The qualifier logic will disable the com-
mands to the ISA devices during the ROM cycles so
that the ISA devices will not respond to ROM cycles. In
addition to this hardware, software should program the
fast ROM chip selects as address decodes only, not
qualified with the command (this is done at Index reg-
isters B3H and B8H). ISA devices that use BALE
should not generate MEMCS16 and/or IOCS16 even if
the above workaround is used, unless the conditions in
the sections above are also met.
ISA MASTER DEVICE ISSUE
ISA master is used by ISA devices that are capable of
taking over the bus and transferring data to and from
other devices without the CPU’s involvement. Not all
ISA devices are capable of Master mode.
The élanSC300 and SC310 devices do not support
ISA master devices because there is no MASTER pin
on the chips. Therefore, only ISA devices that do not
need Master mode to operate should be selected for
system designs.
ISA REFRESH CYCLE ISSUE
The élanSC300 and SC310 microcontrollers do not
support refresh on the ISA bus. There is no REF signal.
The lack of the REF signal could potentially cause two
problems: devices that need the refresh function to re-
fresh their own memory, and devices that need the re-
fresh function to know which ISA cycles to ignore.
The first case–devices that use the ISA REF signal to
do their own memory refreshes—is rare (perhaps non-
existent). If a device has a built-in memory controller, it
will likely also have refresh timing logic.
In the case of devices that use the REF signal to ignore
the ISA cycle because it is a refresh, the lack of a REF
signal is not a problem. The élanSC300 and SC310 mi-
crocontrollers do not do refresh cycles on the ISA bus,
so devices do not need to qualify MEMR with the REF
signal. Any access the device decodes in its address
range is a real access to it and should be acknowledged.
ZERO WAIT STATE TIMING ISSUE
The ISA Zero Wait State signal allows an ISA device to
force commands to occur at zero wait states, thus
speeding up the interface.
However, the élanSC300 and SC310 microcontrollers
require the Zero Wait State signal to be returned faster
than the ISA specification allows. The ISA spec allows
40 nsec from the falling edge of the command to return
the Zero Wait State signal. The élanSC300 and SC310
devices require the signal returned in 20 nsec when the
CPU is clocked at 33 MHz. If the Zero Wait State signal
is missed by the élanSC300 and SC310 devices, the
ISA device will still work but will not be operating at zero
wait speed.
Summary
: Select ISA devices that will return Zero
Wait State in time, or do not use the Zero Wait State
feature.
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