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參數(shù)資料
| 型號(hào)： | 2064VE |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| 中文描述： | 3.3在系統(tǒng)可編程高密度PLD的超快⑩ |
| 文件頁(yè)數(shù)： | 9/15頁(yè) |
| 文件大?。?/td> | 200K |
| 代理商： | 2064VE |
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9
Specifications
ispLSI 2064VE
Power Consumption
Power consumption in the ispLSI 2064VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms
used. Figure 3 shows the relationship between power
and operating speed.
Figure 3. Typical Device Power Consumption vs fmax
0127/2064VE
ICC can be estimated for the ispLSI 2064VE using the following equation:
ICC(mA) = 8 + (# of PTs * 0.67) + (# of Nets * Max. Freq. * 0.0045)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB
loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating
conditions and the program in the device, the actual ICC should be verified.
Notes: Configuration of four 16-bit counters
Typical current at 3.3V, 25
°
C
100
140
0
50
100
150
200
f
max (MHz)
ispLSI 2064VE
160
120
80
I
C
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