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參數(shù)資料
| 型號： | 2064VE |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V In-System Programmable High Density SuperFAST⑩ PLD |
| 中文描述： | 3.3在系統(tǒng)可編程高密度PLD的超快⑩ |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 200K |
| 代理商： | 2064VE |
7
Specifications
ispLSI 2064VE
Internal Timing Parameters
1
Over Recommended Operating Conditions
t
io
t
din
GRP
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036/2064VE
Inputs
UNITS
-135
-200
MIN.
-100
MIN.
MAX.
MIN. MAX.
MAX.
DESCRIPTION
#
2
PARAMETER
20 Input Buffer Delay
21 Dedicated Input Delay
ns
ns
t
grp
GLB
t
4ptbpc
t
4ptbpr
22 GRP Delay
ns
t
1ptxor
t
20ptxor
t
xoradj
t
gbp
t
gsu
t
gh
t
gco
t
gro
t
ptre
t
ptoe
t
ptck
ORP
t
orp
t
orpbp
Outputs
25 1 Product Term/XOR Path Delay
26 20 Product Term/XOR Path Delay
27 XOR Adjacent Path Delay
28 GLB Register Bypass Delay
ns
ns
ns
ns
29 GLB Register Setup Time before Clock
30 GLB Register Hold Time after Clock
ns
ns
31 GLB Register Clock to Output Delay
ns
3
32 GLB Register Reset to Output Delay
33 GLB Product Term Reset to Register Delay
34 GLB Product Term Output Enable to I/O Cell Delay
35 GLB Product Term Clock Delay
ns
ns
ns
ns
t
ob
t
sl
t
oen
t
odis
t
goe
Clocks
38 Output Buffer Delay
39 Output Slew Limited Delay Adder
40 I/O Cell OE to Output Enabled
41 I/O Cell OE to Output Disabled
42 Global Output Enable
ns
ns
ns
ns
ns
23 4 Product Term Bypass Path Delay (Combinatorial)
24 4 Product Term Bypass Path Delay (Registered)
ns
ns
36 ORP Delay
37 ORP Bypass Delay
ns
ns
t
gy0
t
gy1/2
Global Reset
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line
ns
ns
t
gr
45 Global Reset to GLB
0.5
1.1
0.6
2.9
2.9
2.9
0.0
–
–
0.3
0.4
4.3
3.9
4.0
1.5
2.0
3.0
3.0
2.0
1.4
1.9
1.5
0.5
1.2
1.4
3.6
–
–
–
–
–
–
–
1.2
1.8
–
–
–
–
1.0
–
–
–
–
–
–
–
–
–
1.2
1.4
–
0.5
1.7
1.2
4.7
4.7
4.7
0.5
–
–
0.3
1.1
6.1
6.9
5.0
1.6
2.0
3.4
3.4
3.6
3.7
3.7
1.5
0.5
1.6
1.8
5.8
–
–
–
–
–
–
–
1.2
3.8
–
–
–
–
1.6
–
–
–
–
–
–
–
–
–
1.6
1.8
–
0.7
2.5
1.8
6.2
6.2
6.2
1.0
–
–
0.3
3.1
7.1
9.1
5.6
1.6
2.0
3.4
3.4
5.6
5.2
4.7
1.7
0.7
2.4
2.6
7.1
–
–
–
–
–
–
–
1.7
4.8
–
–
–
–
2.6
–
–
–
–
–
–
–
–
–
2.4
2.6
–
ns
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