參數(shù)資料
型號(hào): 16F877
廠商: Microchip Technology Inc.
英文描述: CAT 5E CROSSOVER PATCH CORD CABLE GREEN 20 FT
中文描述: 28/40-pin 8位CMOS閃存微控制器
文件頁(yè)數(shù): 29/200頁(yè)
文件大?。?/td> 3544K
代理商: 16F877
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1999 Microchip Technology Inc.
DS30292B-page 29
PIC16F87X
3.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro
Mid-Range
(DS33023).
Reference
Manual,
3.1
PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corre-
sponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and analog V
REF
input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 3-1:
BCF
BCF
CLRF
INITIALIZING PORTA
STATUS, RP0
;
STATUS, RP1
; Bank0
PORTA
; Initialize PORTA by
; clearing output
; data latches
STATUS, RP0
; Select Bank 1
0x06
; Configure all pins
ADCON1
; as digital inputs
0xCF
; Value used to
; initialize data
; direction
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
BSF
MOVLW
MOVWF
MOVLW
MOVWF
FIGURE 3-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 3-2:
BLOCK DIAGRAM OF RA4/
T0CKI PIN
Note:
On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
Data
Bus
Q
D
Q
CK
Q
D
Q
CK
Q
D
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
V
SS
V
DD
I/O pin
(1)
Note 1:
I/O pins have protection diodes to V
DD
and V
SS
.
Analog
Input
Mode
TTL
Input
Buffer
To A/D Converter
Data
Bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Input
Buffer
N
V
SS
I/O pin
(1)
TMR0 clock input
Q
D
Q
CK
Q
D
Q
CK
EN
Q
D
EN
Note 1:
I/O pin has protection diodes to V
SS
only.
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