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參數(shù)資料
| 型號(hào)： | 13715-806-XTD |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 300 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, GREEN, SOIC-16 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 582K |
| 代理商： | 13715-806-XTD |
FS714x Programmable Phase-Locked Loop Clock Generator
Data Sheet
5.1.3. STOP Data Transfer
A low to high transition of the SDA line while SCL input is high indicates a STOP condition. All commands to the device must be
followed by a STOP condition.
5.1.4. Data Valid
The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START
condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per
data bit.
Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred
between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is
overwritten to the device after the first eight bytes will overflow into the first register, then the second, and so on, in a first-in, first-
overwritten fashion.
5.1.5. Acknowledge
When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must
generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the
high period of the master acknowledge clock pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked)
out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
5.2 I
2C-bus Operation
All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The crystal
oscillator does not have to run for communication to occur.
The device accepts the following I
2C-bus commands:
5.2.1. Slave Address
After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the
device is:
A6
A5
A4
A3
A2
A1
A0
1
0
1
0
X
where X is controlled by the logic level at the ADDR pins. The selectable ADDR bits allow four different FS7140 devices to exist on the
same bus. Note that every device on an I
2C-bus must have a unique address to avoid possible bus conflicts.
5.2.2. Random Register Write Procedure
Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted
after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the
slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an
acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned
by the device, and the master generates a STOP condition.
If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.
7
AMI Semiconductor – Dec, 2007 – Rev. 4.0
www.amis.com
Specifications subject to change without notice
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