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參數資料
| 型號： | 1032EA |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Shielding Material:Aluminum Foil/Polyester Tape/Tinned Copper Braid; Number of Pairs:4 RoHS Compliant: Yes |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁數： | 9/16頁 |
| 文件大小： | 198K |
| 代理商： | 1032EA |
9
Specifications
ispLSI 1032EA
UA
NN
2.8
t
ob
t
sl
1. Internal Timing Parameters are not tested and are for reference only.
Table 2-0037A/1032EA
v.2.4
Outputs
UNITS
-170
MIN.
MIN.
MAX.
MAX.
DESCRIPTION
#
PARAM.
50 Output Buffer Delay
51 Output Buffer Delay, Slew Limited Adder
ns
ns
t
oen
t
odis
t
goe
52 I/O Cell OE to Output Enabled
53 I/O Cell OE to Output Disabled
54 Global OE
ns
ns
ns
t
gy0
t
gy1/2
t
gcp
t
ioy2/3
t
iocp
55 Clock Delay, Y0 to Global GLB Clock Line (Ref. clk)
ns
Global Reset
t
gr
Clocks
60 Global Reset to GLB and I/O Registers
ns
56 Clock Delay, Y1 or Y2 to Global GLB Clock Line
57 Clock Delay, Clock GLB to Global GLB Clock Line
58 Clock Delay, Y2 or Y3 to I/O Cell Global Clock Line
59 Clock Delay, Clock GLB to I/O Cell Global Clock Line
ns
ns
ns
ns
-200
—
—
—
—
—
0.9
0.9
0.8
0.0
0.8
—
0.9
5.0
3.1
3.1
1.4
0.9
0.0
0.9
1.8
0.0
2.8
—
—
—
—
—
0.9
0.9
0.8
0.0
0.8
—
1.1
5.0
3.5
3.5
2.9
0.9
0.4
0.9
1.8
0.0
Internal Timing Parameters
1
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