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參數(shù)資料
| 型號(hào)： | 1032EA |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Shielded Paired Cable; Number of Conductors:8; Conductor Size AWG:24; No. Strands x Strand Size:7 x 32; Jacket Material:Polyethylene; Shielding Material:Aluminum Foil/Polyester Tape/Tinned Copper Braid; Number of Pairs:4 RoHS Compliant: Yes |
| 中文描述： | 在系統(tǒng)可編程高密度可編程邏輯器件 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 198K |
| 代理商： | 1032EA |
12
Specifications
ispLSI 1032EA
ispLSI 1032EA Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
0491/1032EA
Feedback
#47
Reg 4 PT Bypass
#35
20 PT
XOR Delays
Control
PTs
#44 - 46
Input
RST
DiClock
I/O Pin
(Input)
Y0
Y1,2,3
D
Q
GRP4
#30
GLB Reg Bypass
#39
ORP Bypass
#49
D
Q
RST
RE
OE
CK
I/O Reg Bypass
#22
I/O Cell
ORP
GLB
GRP
I/O Cell
#23 - 27
#34 Comb 4 PT Bypass
#36 - 38
#56 - 59
#55
#54
#48
Reset
Ded. In
GOE 0,1
#28
#60
#60
#40 - 43
#52, 53
#50, 51
GRP Loading
Delay
#29, 31 - 33
Derivations of
t
su,
t
h and
t
co from the Product Term Clock
1
=
=
=
=
(0.3 + 1.5 + 1.9) + (0.2) - (0.3 + 1.5 + 1.5)
0.6
t
su
Logic + Reg su - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) - (
t
iobp +
t
grp4 +
t
ptck(min))
(#22 + #30 + #37) + (#40) - (#22 + #30 + #46)
1.6
7.4
0.8
1.4
7.2
=
=
=
=
t
h
Clock (max) + Reg h - Logic
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gh) - (
t
iobp +
t
grp4 +
t
20ptxor)
(#22 + #30 + #46) + (#41) - (#22 + #30 + #37)
(0.3 + 1.5 + 2.5) + (1.0) - (0.3 + 1.5 + 1.9)
=
=
=
=
t
co
Clock (max) + Reg co + Output
(
t
iobp +
t
grp4 +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#22 + #30 + #46) + (#42) + (#48 + #50)
(0.3 + 1.5 + 2.5) + (1.4) + (0.8 + 0.9)
Table 2-0042a/1024EA
v.2.5
Derivations of
t
su,
t
h and
t
co from the Clock GLB
1
=
=
=
=
t
su
Logic + Reg (setup) - Clock (min)
(
t
iobp +
t
grp4 +
t
20ptxor) + (
t
gsu) - (
t
gy0(min) +
t
gco +
t
gcp(min))
(#22 + #30 + #37) + (#40) - (#55 + #42 + #57)
(0.3 + 1.5 + 1.9) + (0.2) - (0.9 + 1.4 + 0.8)
=
=
=
=
t
h
Clock (max) + Reg (hold) - Logic
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gh) - (
t
iobp +
t
grp4 +
t
20ptxor)
(#55 + #42 + #57) + (#41) - (#22 + #30 + #37)
(0.9 + 1.4 + 1.8) + (1.0) - (0.3 + 1.5 + 1.9)
=
=
=
=
t
co
Clock (max) + Reg (clock-to-out) + Output
(
t
gy0(max) +
t
gco +
t
gcp(max)) + (
t
gco) + (
t
orp +
t
ob)
(#55 + #42 + #57) + (#42) + (#48 + #50)
(0.9 + 1.4 + 1.8) + (1.4) + (0.8 + 0.9)
1. Calculations are based upon timing specifications for the ispLSI 1032EA-200.
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