BELASIGNA 250
http://onsemi.com
24
Figure 10. Power Management
ShutDown
PowerOn
Reset
PowerOn
Reset
VDDC
TPOR
VDDCnominal
VDDCstartup
VDDCshutdown
Internal Reset Signal
Normal PowerUp
Transient
Dying Battery
Time
Other Analog Support Blocks and Functions
MultiChip Sample Clock (MCLK) Synchronization
BELASIGNA 250 allows MCLK synchronization
between two or more BELASIGNA 250 devices connected
in a multichip configuration. Samples on multiple chips
will synchronize to occur at the same instant in time. This is
useful in applications using microphone arrays where
synchronous sampling is required. The sample clock
synchronization is enabled using a control bit and a GPIO
assignment that brings all MCLKs across chips to zero phase
at the same instant in time.
LowSpeed A/D Converters (LSAD)
Six LSAD inputs are available on BELASIGNA 250.
Combined with two internal LSAD inputs (supply and
ground), there are a total of eight multiplexed inputs to the
LSAD converter. The multiplexed inputs are sampled
sequentially at 1.6 kHz per channel when operating at MCLK
of 1.28 MHz (proportionally). The native data format for the
LSAD is 10bit two’scomplement. However, a total of eight
operation modes are provided that allow a configurable input
dynamic range in cases where certain minimum and
maximum values for the converted inputs are desired, such as
in the case of a volume control where only input values up to
a certain magnitude are allowed. The six LSAD pads are
multiplexed with other functionality.
Battery Monitor
A programmable onchip battery monitor is available for
power management. The battery monitor works by
incrementing a counter value every time the battery voltage
goes below a desired, configurable threshold value. This
counter value can be used in an applicationspecific
powermanagement algorithm running on the RCore. The
RCore can initiate any desired actions in case the battery hits
a predetermined value. This function is realized with an
internal LSAD tied directly to the power supply.
Infrared (IR) Remote Control
A switchedcarrier IR remote control receiver interface is
provided, which can receive commands wirelessly with the
attachment of a photovoltaic diode or similar component. Data
transfer from a remote unit is initiated by first transmitting a
burst sequence followed by the data to be transferred. The
data must be RS232 formatted (8N1) and must be
modulated using a 40 kHz switchedcarrier modulation
scheme. Data are received at 1200 bps by a dedicated UART.
The remote control receiver interacts with the RCore
through memory mapped control registers and interrupts.
This interface is not available on the 5 x 5 CABGA
package.
Digital Interfaces
BELASIGNA 250 has the following digital interfaces:
16pin generalpurpose I/O (GPIO) interface.
Serial peripheral interface (SPI) communications port
with interface speeds up to 640 kbps at 1.28 MHz
system clock. The SPI port on BELASIGNA 250 only
supports master mode, so it will only communicate with
SPI slave devices. When connecting to an SPI slave
device other than a boot EEPROM, the SPI_CS pin
should be left unconnected and the slave device CS line
should be driven from a GPIO to avoid
BELASIGNA 250 boot malfunction. When connecting