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參數(shù)資料
| 型號： | 05F6928 |
| 英文描述： | IC-ANALOGUE MULTIPLIER |
| 中文描述： | 集成電路模擬乘法器 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 347K |
| 代理商： | 05F6928 |
AD524
REV. C
–7–
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an auto-zero cycle, but there are many small-
signal high-gain applications that don’t have this capability.
Voltage offset and drift comprise two components each; input
and output offset and offset drift. Input offset is that component
of offset that is directly proportional to gain i.e., input offset as
measured at the output at G = 100 is 100 times greater than at
G = 1. Output offset is independent of gain. At low gains, out-
put offset drift is dominant, while at high gains input offset drift
dominates. Therefore, the output offset voltage drift is normally
specified as drift at G = 1 (where input effects are insignificant),
while input offset voltage drift is given by drift specification at a
high gain (where output offset effects are negligible). All input-
related numbers are referred to the input (RTI) which is to say
that the effect on the output is “G” times larger. Voltage offset
vs. power supply is also specified at one or more gain settings
and is also RTI.
By separating these errors, one can evaluate the total error inde-
pendent of the gain setting used. In a given gain configuration
both errors can be combined to give a total error referred to the
input (R.T.I.) or output (R.T.O.) by the following formula:
Total Error R.T.I. = input error + (output error/gain)
Total Error R.T.O. = (Gain
× input error) + output error
As an illustration, a typical AD524 might have a +250
V out-
put offset and a –50
V input offset. In a unity gain configura-
tion, the total output offset would be 200
V or the sum of the
two. At a gain of 100, the output offset would be –4.75 mV or:
+250
V + 100(–50 V) = –4.75 mV.
The AD524 provides for both input and output offset adjust-
ment. This simplifies very high precision applications and mini-
mize offset voltage changes in switched gain applications. In
such applications the input offset is adjusted first at the highest
programmed gain, then the output offset is adjusted at G = 1.
GAIN
The AD524 has internal high accuracy pretrimmed resistors for
pin programmable gain of 1, 10, 100 and 1000. One of the pre-
set gains can be selected by pin strapping the appropriate gain
terminal and RG2 together (for G = 1 RG2 is not connected).
7
–Vs
8
+Vs
AD524
6
10
9
RG2
16
13
12
11
3
2
1
G = 10
G = 100
G = 1000
5
4
VOUT
OUTPUT
SIGNAL
COMMON
INPUT
OFFSET
NULL
10k
RG1
+INPUT
–INPUT
Figure 30. Operating Connections for G = 100
The AD524 can be configured for gains other than those that
are internally preset; there are two methods to do this. The first
method uses just an external resistor connected between pins 3
and 16 which programs the gain according to the formula
RG =
40k
G
= –1
(see Figure 31). For best results RG should be a
precision resistor with a low temperature coefficient. An external
RG affects both gain accuracy and gain drift due to the mismatch
between it and the internal thin-film resistors. Gain accuracy is
determined by the tolerance of the external RG and the absolute
accuracy of the internal resistors (
±20%). Gain drift is determined
by the mismatch of the temperature coefficient of RG and the
temperature coefficient of the internal resistors (– 50 ppm/
°C typ).
7
–Vs
8
+Vs
AD524
6
10
9
RG2
16
13
12
11
3
2
1
VOUT
REFERENCE
RG1
+INPUT
–INPUT
1.5k
1k
OR
2.105k
40,000
2.105
G =
+1 = 20
± 20%
Figure 31. Operating Connections for G = 20
The second technique uses the internal resistors in parallel with
an external resistor (Figure 32). This technique minimizes the
gain adjustment range and reduces the effects of temperature
coefficient sensitivity.
7
–Vs
8
+Vs
AD524
6
10
9
RG2
16
13
12
11
3
2
1
VOUT
REFERENCE
RG1
+INPUT
–INPUT
4k
40,000
4000/4444.44
G =
+1 = 20
± 17%
G = 10
R|G = 10 = 4444.44
R|G = 100 = 404.04
R|G = 1000 = 40.04
NOMINAL (
±20%)
*
Figure 32. Operating Connections for G = 20, Low Gain
T.C. Technique
The AD524 may also be configured to provide gain in the out-
put stage. Figure 33 shows an H pad attenuator connected to
the reference and sense lines of the AD524. R1, R2 and R3
should be made as low as possible to minimize the gain variation
and reduction of CMRR. Varying R2 will precisely set the gain
without affecting CMRR. CMRR is determined by the match of
R1 and R3.
7
–Vs
8
+Vs
AD524
6
10
9
RG2
16
13
12
11
3
2
1
G = 10
G = 100
G = 1000
VOUT
RG1
+INPUT
–INPUT
R2
5k
R3
2.26k
RL
R1
2.26k
G =
(R2||40k) + R1 + R3
(R2||40k)
(R1 + R2 + R3)||RL≥2k
Figure 33. Gain of 2000
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