21
6-22.
Key Return Mode Register Format.....................................................................................
145
7-1.
7-2.
7-3.
7-4.
7-5.
7-6.
7-7.
7-8.
7-9.
7-10.
Clock Generator Block Diagram .........................................................................................
Subsystem Clock Feedback Resistor.................................................................................
Processor Clock Control Register Format ..........................................................................
Oscillation Mode Selection Register Format ......................................................................
Main System Clock Waveform due to Writing to OSMS.....................................................
External Circuit of Main System Clock Oscillator ...............................................................
External Circuit of Subsystem Clock Oscillator ..................................................................
Examples of Oscillator with Bad Connection......................................................................
Main System Clock Stop Function .....................................................................................
System Clock and CPU Clock Switching ...........................................................................
150
151
152
154
154
155
156
156
160
164
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
16-bit Timer/Event Counter Block Diagram ........................................................................
16-bit Timer/Event Counter Output Control Circuit Block Diagram ....................................
Timer Clock Select Register 0 Format................................................................................
16-bit Timer Mode Control Register Format .......................................................................
Capture/Compare Control Register 0 Format.....................................................................
16-bit Timer Output Control Register Format .....................................................................
Port Mode Register 3 Format .............................................................................................
External Interrupt Mode Register 0 Format ........................................................................
Sampling Clock Select Register Format.............................................................................
Control Register Settings for Interval Timer Operation.......................................................
Interval Timer Configuration Diagram.................................................................................
Interval Timer Operation Timings .......................................................................................
Control Register Settings for PWM Output Operation ........................................................
Example of D/A Converter Configuration with PWM Output ..............................................
TV Tuner Application Circuit Example ................................................................................
Control Register Settings for PPG Output Operation .........................................................
Control Register Settings for Pulse Width Measurement with
Free-Running Counter and One Capture Register.............................................................
Configuration Diagram for Pulse Width Measurement by Free-Running Counter .............
Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified) ....................................................
Control Register Settings for Two Pulse Width Measurements
with Free-Running Counter ................................................................................................
Timing of Pulse Width Measurement Operation with
Free-Running Counter (with Both Edges Specified) ..........................................................
Control Register Settings for Pulse Width Measurement with
Free-Running Counter and Two Capture Registers ...........................................................
Timing of Pulse Width Measurement Operation by Free-Running
Counter and Two Capture Registers (with Rising Edge Specified) ....................................
Control Register Settings for Pulse Width Measurement by Means of Restart ..................
170
171
174
176
177
179
180
181
182
183
184
184
186
187
187
188
189
190
8-18.
8-19.
190
8-20.
191
8-21.
192
8-22.
193
8-23.
194
195
8-24.
LIST OF FIGURES (2/8)
Figure No.
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