441
APPENDIX E REVISION HISTORY
(3/3)
Edition No.
Main revised contents from old edition
Revised Sections
4th Edition
Addition of caution regarding setting values for memory size switching register
to
5.1 Memory Spaces
Change and addition of
Caution
to
8.3 16-bit Timer/Event Counter Configu-
ration (2) Capture/compare register00(CR00), (3) Capture/compare
register01(CR01)
Change in
Figure 8-2 16-bit Timer Mode Control Register (TMC0) Format
Addition of
Caution
to
Figure 8-3 Capture/Compare Control Register 0
(CRC0) Format
Addition of
Note
to
Figure 8-4 16-bit Timer Output Control Register (TOC0) Format
Change and addition of
Caution
to
Figure 8-5 Prescaler Mode Register 0
(PRM0) Format
Addition of
Caution
to
Figure 8-10 Control Register Settings for PPG Output
Operation
Addition of
Caution
to
Figure 8-10 Control Register Settings for PPG Output
Operation
Revision of following timing charts
Figure 8-13 Timing of Pulse Width Measurement Operation by Free-
Running Counter and One Capture Register (with Both Edges Specified)
Figure 8-16 Timing of Pulse Width Measurement Operation with Free-
Running Counter (with Both Edges Specified)
Figure 8-18 Timing of Pulse Width Measurement Operation by Free-Running
Counter and Two Capture Registers (with Rising Edge Specified)
Figure 8-20 Timing of Pulse Width Measurement Operation by Means of
Restart (with Rising Edge Specified)
Addition of
Caution
to
8.5.4 External event counter operation
8.5.6 One-shot pulse output operation
First sentence about prohibition of one-shot pulse output with external trigger
completely changed
8.6 16-bit Timer/Event Counter Operating Precautions
Revision in
(7) Operation of OVF0 flag
Addition of the following items
(9) Timer operation
(10) Capture operation
(11) Compare operation
(12) Edge detection
Revision of
Caution
of
13.2 A/D Converter Configuration, (2) A/D conversion
result register (ADCR0)
Revision in
13.5 A/D Converter Cautions, (10) A/D conversion result register
(ADCR0) read operation
Revision of
Caution
of
14.2 A/D Converter Configuration, (2) A/D conversion
result register (ADCR0)
Revision in
14.5 A/D Converter Cautions, (10) A/D conversion result register
(ADCR0) read operation
Addition of
Note
to
Figure 17-2 Serial Interface (SIO30) Configuration
Revision of
18.3 Registers to Control Serial Interface, (1) IIC control register
(IICC0)
Revision of explanations of STT0 and SPT0 flags in
Figure 18-3 IIC Control
Register (IICC0) Format
CHAPTER 5 CPU
ARCHITECTURE
CHAPTER 8 16-BIT
TIMER/EVENT
COUNTER
CHAPTER 13 8-BIT A/D
CONVERTER
(
μ
PD780024, 780024Y
SUBSERIES)
CHAPTER 14 10-BIT A/
D CONVERTER
(
μ
PD780034, 780034Y
SUBSERIES)
CHAPTER 17 SERIAL
INTERFACE (SIO3)
CHAPTER 18 SERIAL
INTERFACE (IIC0)
(
μ
PD780024Y, 780034Y
SUBSERIES ONLY)