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CHAPTER 18 SERIAL INTERFACE (IIC0) (
μ
PD780024Y, 780034Y SUBSERIES ONLY)
Figure 18-3. IIC Control Register (IICC0) Format (1/3)
Address: FFA8H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
IICC0
IICE0
LREL0
WREL0
SPIE0
WTIM0
ACKE0
STT0
SPT0
IICE0
I
2
C operation enable
0
Stops operation. Presets expansion register (IICS0). Stops internal operation.
1
Enables operation.
Condition for clearing (IICE0 = 0)
Condition for setting (IICE0 = 1)
Cleared by instruction
When RESET is input
Set by instruction
LREL0
Exit from communications
0
Normal operation
1
This exits from the current communications operation and sets standby mode. This setting is
automatically cleared after being executed. Its uses include cases in which a locally irrelevant
extension code has been received.
The SCL0 and SDA0 lines go into the high impedance state.
The following flags are cleared.
STD0 ACKD0 TRC0 COI0 EXC0 MSTS0 STT0 SPT0
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
After a stop condition is detected, restart is in master mode.
An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0)
Note
Condition for setting (LREL0 = 1)
Automatically cleared after execution
When RESET is input
Set by instruction
WREL0
Cancel wait
0
Does not cancel wait
1
Cancels wait. This setting is automatically cleared after wait is canceled.
Condition for clearing (WREL0 = 0)
Note
Condition for setting (WREL0 = 1)
Automatically cleared after execution
When RESET is input
Set by instruction
SPIE0
Enable/disable generation of interrupt request when stop condition is detected
0
Disable
1
Enable
Condition for clearing (SPIE0 = 0)
Note
Condition for setting (SPIE0 = 1)
Cleared by instruction
When RESET is input
Set by instruction
Note
This flag’s signal is invalid when IICE0 = 0.