107
CHAPTER 5 CPU ARCHITECTURE
Address
Special-Function Register (SFR) Name
Symbol
R/W
After Reset
FFA8H
IIC control register
Note 1
IICC0
R/W
√
√
—
00H
FFA9H
IIC status register
Note 1
IICS0
R
√
√
—
FFAAH
IIC clock selection register
Note 1
IICCL0
R/W
√
√
—
FFABH
Slave address register
Note 1
SVA0
—
√
—
FFB0H
Serial operation mode register 30
CSIM30
√
√
—
FFB8H
Serial operation mode register 31
Note 2
CSIM31
√
√
—
FFD0H
↓
FFDFH
External access area
Note 3
√
√
—
Undefined
FFE0H
Interrupt request flag register 0L
IF0
IF0L
√
√
√
00H
FFE1H
Interrupt request flag register 0H
IF0H
√
√
FFE2H
Interrupt request flag register 1L
IF1L
√
√
—
FFE4H
Interrupt mask flag register 0L
MK0
MK0L
√
√
√
FFH
FFE5H
Interrupt mask flag register 0H
MK0H
√
√
FFE6H
Interrupt mask flag register 1L
MK1L
√
√
—
FFE8H
Priority level specification flag register 0L
PR0
PR0L
√
√
√
FFE9H
Priority level specification flag register 0H
PR0H
√
√
FFEAH
Priority level specification flag register 1L
PR1L
√
√
—
FFF0H
Memory size switching register
IMS
—
√
—
CFH
Note 4
FFF8H
Memory expansion wait setting register
MM
√
√
—
10H
FFF9H
Watchdog timer mode register
WDTM
√
√
—
00H
FFFAH
Oscillation stabilization time selection register
OSTS
—
√
—
04H
FFFBH
Processor clock control register
PCC
√
√
—
Table 5-5. Special-Function Register List (3/3)
Manipulatable Bit Unit
16 bits
8 bits
1 bit
Notes 1.
μ
PD780024Y, 780034Y Subseries only
2.
μ
PD780024, 780034 Subseries only
3.
The external access area cannot be accessed by SFR addressing. Access it with the direct addressing
method.
4.
The default is CFH, but set the value corresponding to each respective product as indicated below.
μ
PD780021, 780031, 780021Y, 780031Y: 42H
μ
PD780022, 780032, 780022Y, 780032Y: 44H
μ
PD780023, 780033, 780023Y, 780033Y: C6H
μ
PD780024, 780034, 780024Y, 780034Y: C8H
μ
PD78F0034, 780034Y: Value for mask ROM version