- vii -
LIST OF FIGURES (4/4)
Figure No.
Title
Page
10-1.
Format of Display Mode Register 0 (
μ
PD78044F and
μ
PD78044H Subseries) ............ 251
Format of Display Mode Register 0 (
μ
PD780208 Subseries)......................................... 252
Format of Display Mode Register 0 (
μ
PD780228 Subseries)......................................... 254
Format of Display Mode Register 1 (
μ
PD78044F and
μ
PD78044H Subseries) ............ 255
Format of Display Mode Register 1 (
μ
PD780208 Subseries)......................................... 256
Format of Display Mode Register 1 (
μ
PD780228 Subseries)......................................... 257
Format of Display Mode Register 2 (
μ
PD780208 Subseries)......................................... 258
Format of Display Mode Register 2 (
μ
PD780228 Subseries)......................................... 260
FIP Controller Operation Timing....................................................................................... 261
10-2.
10-3.
10-4.
10-5.
10-6.
10-7.
10-8.
10-9.
10-10.
Configuration of 12-Digit FIP Display and Key Input....................................................... 262
10-11.
Pin Layout for 9-Segment Display.................................................................................... 264
10-12.
Relationship between Contents of Display Data Memory and Segment Output ........... 265
10-13.
Display Example................................................................................................................ 266
10-14.
Key Interrupt Timing Chart ............................................................................................... 267
10-15.
Compensating for Chattering............................................................................................ 268
11-1.
Block Diagram of 6-Bit Up/Down Counter ....................................................................... 275
11-2.
Format of 6-Bit Up/Down Counter Control Register........................................................ 276