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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
μ
PD78018FY SUBSERIES)
Table 16-4. Generation of Interrupt Request Signal by Serial Interface Channel 0
Serial Transfer Mode
BSYE
WUP
WAT1
WAT0
ACKE
Description
3-wire serial I/O mode
or
0
0
0
0
0
Generates interrupt request signal each time
serial clock is counted eight times
2-wire serial I/O mode
Others
Setting prohibited
I
2
C bus mode
(during transmission)
0
0
1
0
0
Generates interrupt request signal each time
serial clock is counted eight times (8 clock wait).
Normally, setting of WAT1, WAT0 = 1, 0 is not
made during transmission. This setting is used
only when reception and processing must be
systematically arranged by software.
Because ACK information is generated by
reception side, ACKE is set to 0 (disabled).
1
1
0
Generates interrupt request signal each time
serial clock is counted nine times (9 clock wait).
Because ACK information is generated by
reception side, ACKE is set to 0 (disabled).
Others
Setting prohibited
I
2
C bus mode
(during reception)
1
0
1
0
0
Generates interrupt request signal each time
serial clock is counted eight times (8 clock wait).
ACK information is output by manipulating ACKT
by sofrware after interrupts request signal are
generated.
1
1
0/1
Generates interrupt request signal each time
serial clock is counted nine times (9 clock wait).
To generate ACK information automatically,
ACKE is set to 1 (enable) before starting
transfer. However, master sets ACKE to 0
(disable) before receiving last data.
1
1
1
1
1
After receiving an address, generates an
interrupt request signal when the values of the
serial I/O shift register 0 (SIO0) and slave
address register (SVA) coincide, and when the
stop condition is detected.
To generate ACK information automatically,
ACKE is set to 1 (enable) before starting transfer.
Others
Setting prohibited
Remark
BSYE : Bit 7 of serial bus interface control register (SBIC)
ACKE : Bit 5 of serial bus interface control register (SBIC)