285
CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (
μ
PD78018F SUBSERIES)
Notes 1.
Bit 6 (COI) is a read-only bit.
2.
This pin can be freely used for port function.
3.
Clear bit 5 (SIC) of the interrupt timing specification register (SINT) to 0 when using the wake-
up function (WUP = 1).
4.
When CSIE0 = 0, COI is 0.
Remark
×
PM
××
: Port mode register
P
××
: Output latch of port
: Don’t care
<6>
<5>
4
3
2
1
0
<7>
Symbol
CSIM0 CSIE0
COI
WUP
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM01
0
1
Selects clock of serial interface channel 0
Clock externally input to SCK0 pin
Output of 8-bit timer register 2 (TM2)
3-wire serial I/O mode (Refer to
15.4.2 Operation in 3-wire serial I/O mode
.)
0
SCK0
(CMOS l/O)
R/W
1
Clock specified by bits 0-3 of timer clock select register 3 (TCL3)
CSIM
04
0
2-wire serial I/O mode (Refer to
15.4.4 Operation in 2-wire serial I/O mode
.)
1
1
CSIM00
×
0
1
FF60H 00H R/W
Note 1
Address On reset R/W
R/W
CSIM
03
CSIM
02
PM25 P25 PM26 P26 PM27 P27
Operation
mode
First bit
SI0/SB0/P25
pin function
SO0/SB1/P26
pin function
SCK0/P27
pin function
×
1
1
0
×
0
×
0
0
×
0
×
0
0
1
1
Note 2
Note 2 Note 2
SBI mode
MSB
P25 (CMOS I/O)
SB0
(N-ch open
drain I/O)
SB1
(N-ch open
drain I/O)
P26 (CMOS I/O)
WUP
0
1
Controls wake-up function
Generates interrupt request signal in all modes each time serial transfer is executed
Generates interrupt request signal when address received after bus has been released in SBI mode (when
CMDD = RELD = 1) coincides with data of slave address register (SVA)
R/W
COI
0
Slave address comparison result flag
Note 4
Data of slave address register (SVA) does not coincide with data of serial l/O shift register 0 (SIO0)
Data of slave address register (SVA) coincides with data of serial l/O shift register 0 (SIO0)
R
1
CSIE0
0
Controls operation of serial interface channel 0
Stops operation
Enables operation
R/W
1
Note 2
Note 3