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CHAPTER 5 CPU ARCHITECTURE
(c) Register bank select flags (RBS0 and RBS1)
These 2-bit flags select one of the four register banks.
Information of 2 bits that indicate the register bank selected by execution of the “SEL RBn” instruction
is stored in these flags.
(d) Auxiliary carry flag (AC)
This flag is set to 1 when a carry occurs from bit 3 or a borrow to bit 3 occurs as a result of an operation
performed; otherwise, it is reset to 0.
(e) In-service priority flag (ISP)
This flag controls the priority of maskable vectored interrupts that can be acknowledged.
When ISP = 0, the vectored interrupt which is assigned a low priority by the priority specification flag
registers (PR0L and PR0H) (refer to
18.3 (3) Priority specification flag registers (PR0L, PR0H)
)should
not be accepted. Whether the interrupt is actually accepted is controlled by the status of the interrupt
enable flag (IE).
(f)
Carry flag (CY)
This flag records an overflow or underflow that occurs as the result of executing an add or subtract
instruction. It also records the value shifted out when a rotate instruction is executed. In addition, it also
functions as a bit accumulator when a bit operation instruction is executed.
(3) Stack pointer (SP)
This is a 16-bit register that holds the first address of the stack area in the memory. As the stack area, only
the internal high-speed RAM area can be specified. The internal high-speed RAM area of each product is
as follows:
Table 5-5. Internal High-Speed RAM Area
Part Number
Internal High-Speed RAM Area
μ
PD78011F, 78011FY, 78012F, 78012FY
FD00H-FEFFH
μ
PD78013F, 78013FY, 78014F, 78014FY
FB00H-FEFFH
μ
PD78015F, 78015FY, 78016F, 78016FY
μ
PD78018F, 78018FY, 78P018F, 78P018FY
Figure 5-11. Stack Pointer Configuration
SP15 SP14 SP13 SP12 SP11 SP10
SP9 SP8
SP
SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
15
The contents of the stack pointer are decremented when data is written (saved) to the stack memory, and
incremented when data are read (restored) from the stack memory.
The data saved/restored as a result of each stack operation are as shown in Figures 5-12 and 5-13.
Caution The contents of the SP become undefined when the RESET signal is input. Be sure to
initialize the SP before executing an instruction.