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參數(shù)資料
| 型號(hào)： | μPD75P70076 |
| 廠商： | NEC Corp. |
| 英文描述： | 4 Bit Single Chip Microcontrollers(4位單片微控制器) |
| 中文描述： | 4位單片微控制器（4位單片微控制器） |
| 文件頁數(shù)： | 13/62頁 |
| 文件大?。?/td> | 290K |
| 代理商： | ΜPD75P70076 |
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m
PD75P0076
13
4. SWITCHING BETWEEN Mk I AND Mk II MODES
Setting a stack bank selection (SBS) register for the
m
PD75P0076 enables the program memory to be switched between
the Mk I mode and the Mk II mode. This capability enables the evaluation of the
m
PD750064, 750066, and 750068 using
the
m
PD75P0076.
When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of
m
PD750064, 750066, and 750068)
When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of
m
PD750064, 750066, and 750068)
4.1 Differences between Mk I Mode and Mk II Mode
Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the
m
PD75P0076.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Item
Mk I Mode
Mk II Mode
Program counter
PC
13 to 0
Program memory (bytes)
16384
Data memory (bits)
512 x 4
Stack
Stack bank
Selectable from memory banks 0 and 1
Stack bytes
2 bytes
3 bytes
Instruction
BRA !addr1
CALLA !addr1
Not provided
Provided
Instruction
CALL !addr
3 machine cycles
4 machine cycles
execution time CALLF !faddr
2 machine cycles
3 machine cycles
Supported mask ROM versions and
mode
Mk I mode of
m
PD750064, 750066,
and 750068
Mk II mode of
m
PD750064, 750066,
and 750068
Caution
The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This
mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call
instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when
a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle.
Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.
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