參數(shù)資料
型號： μPD75P3018A
廠商： NEC Corp.
英文描述： 4 Bit Single Chip Microcontrollers(4位單片微控制器)
中文描述： 4位單片微控制器（4位單片微控制器）
文件頁數(shù)： 8/60頁
文件大小： 337K
代理商： ΜPD75P3018A
μPD75P3018A
8
3.2 Non-port Pins (1/2)
Pin name
I/O
Shared by
Function
Status
after reset
I/O circuit
type
Note 1
TI0
Input
P13
External event pulse input to timer/event counter
Input
<B>-C
TI1, TI2
P12/INT2
PTO0
Output
P20
Timer/event counter output
Input
E-B
PTO1
P21
PTO2
P22
PCL
P22
Clock output
BUZ
P23
Optional frequency output (for buzzer or system clock trimming)
SCK
I/O
P01
Serial clock I/O
Input
<F>-A
SO/SB0
P02
Serial data output
Serial data bus I/O
<F>-B
SI/SB1
P03
Serial data input
Serial data bus I/O
<M>-C
INT4
Input
P00
Edge detection vectored interrupt input
(both rising and falling edges detection)
<B>
INT0
Input
P10
Edge detection vectored interrupt input
(detected edge is selectable)
Noise elimination circuit/
asynchronous is selectable
Input
<B>-C
INT1
P11
INT0/P10 can select noise elimination circuit.
Asynchronous
INT2
P12/TI1/TI2
Rising edge detection testable input
Asynchronous
KR0-KR3
Input
P60-P63
Falling edge detection testable input
Input
<F>-A
KR4-KR7
Input
P70-P73
Falling edge detection testable input
Input
<F>-A
X1
Input
—
Ceramic/crystal oscillation circuit connection for main system
clock. If using an external clock, input to X1 and input
inverted phase to X2.
—
—
X2
—
XT1
Input
—
Crystal oscillation circuit connection for subsystem clock.
If using an external clock, input to XT1 and input inverted
phase to XT2. XT1 can be used as a 1-bit (test) input.
—
—
XT2
—
RESET
Input
—
System reset input (low level active)
—
<B>
MD0
Input
P30/LCDCL
Mode selection for program memory (PROM) write/verify
Input
E-B
MD1
P31/SYNC
MD2, MD3
P32, P33
D0-D3
I/O
P40-P43
Data bus for program memory (PROM) write/verify
Input
M-E
D4-D7
P50-P53
V
PP
Note 2
—
—
Program power supply voltage for program memory
(PROM) write/verify.
For normal operation, connect directly to V
DD
.
Apply +12.5 V for PROM write/verify.
—
—
V
DD
—
—
Positive power supply
—
—
Vss
—
—
Ground
—
—
Notes
2. The V
PP
pin does not operate correctly during normal operation unless connected to the V
DD
pin.
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