參數(shù)資料
型號: μPD45D128442
廠商: NEC Corp.
英文描述: 128 M-bit Synchronous DRAM with Double Data Rate(128 同步動態(tài)RAM)
中文描述: 128 M位同步雙數(shù)據(jù)速率(128同步動態(tài)RAM的內(nèi)存)
文件頁數(shù): 32/80頁
文件大?。?/td> 637K
代理商: ΜPD45D128442
32
μ
PD45D128442, 45D128842, 45D128164
Preliminary Data Sheet
11.3 Write to Read Command Interval
The burst write operation can be interrupted by read command of any bank. The data bus must be high impedance
at least 1 cycle prior to the first output data.
The minimum time interval between the rising clock edge after the last input data and the read command is 1 cycle.
When the read command is issued, the invalid data from the burst write cycle must be masked by DM.
CLK
Write A
DQS
Command
/CAS latency = 2
/CLK
CKE
Read B
DQ
DA1
DM
QB1
QB2
QB3
QB4
Write A
DQS
Command
Read B
DQ
DA1
DA2
DM
QB1
QB2
/CAS latency = 2.5
DQ and DQS : Input
DQ and DQS : Output
DA2
1 cycle
QB3
T0
T2
T1
T3
T4
T5
T6
Hi-Z
Hi-Z
Hi-Z
Hi-Z
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