參數(shù)資料
型號(hào): μPD42S17805L
廠商: NEC Corp.
英文描述: 3.3V OPERATION 16 M-BIT DYNAMIC RAM 2M-WORD BY 8-BIT,EDO
中文描述: 3.3運(yùn)行16位動(dòng)態(tài)隨機(jī)存儲(chǔ)器2m-word8位,江戶
文件頁數(shù): 1/36頁
文件大?。?/td> 307K
代理商: ΜPD42S17805L
1995
DATA SHEET
The mark
shows major revised points.
MOS INTEGRATED CIRCUIT
μ
PD42S17805L, 4217805L
Description
The
μ
PD42S17805L, 4217805L are 2,097,152 words by 8 bits CMOS dynamic RAMs with optional EDO.
EDO is a kind of the page mode and is useful for the read operation.
Besides, the
μ
PD42S17805L can execute CAS before RAS self refresh.
The
μ
PD42S17805L, 4217805L are packaged in 28-pin plastic TSOP (
II
) and 28-pin plastic SOJ.
Features
EDO (Hyper page mode)
2,097,152 words by 8 bits organization
Single +3.3 V
±
0.3 V power supply
Fast access and cycle time
Part number
Power consumption
Active (MAX.)
Access time
(MAX.)
R/W cycle time
(MIN.)
EDO (Hyper page mode)
cycle time (MIN.)
μ
PD42S17805L-A50, 4217805L-A50
432 mW
50 ns
84 ns
20 ns
μ
PD42S17805L-A60, 4217805L-A60
360 mW
60 ns
104 ns
25 ns
μ
PD42S17805L-A70, 4217805L-A70
324 mW
70 ns
124 ns
30 ns
The
μ
PD42S17805L can execute CAS before RAS self refresh
Part number
Refresh cycle
Refresh
Power consumption at
standby (MAX.)
μ
PD42S17805L
2,048 cycles/128 ms
CAS before RAS self refresh,
CAS before RAS refresh,
RAS only refresh, Hidden refresh
0.54 mW
(CMOS level input)
μ
PD4217805L
2,048 cycles/32 ms
CAS before RAS refresh,
RAS only refresh,
Hidden refresh
1.8 mW
(CMOS level input)
Document No. M10070EJ5V0DS00 (5th edition)
Date Published January 1997 N
Printed in Japan
The information in this document is subject to change without notice.
3.3 V OPERATION 16 M-BIT DYNAMIC RAM
2 M-WORD BY 8-BIT, EDO
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