參數(shù)資料
型號: μPD42280
廠商: NEC Corp.
英文描述: 2 M-Bit Field Buffer(2M位現(xiàn)場緩存)
中文描述: 2 m位場緩沖器(200萬位現(xiàn)場緩存)
文件頁數(shù): 1/28頁
文件大?。?/td> 200K
代理商: ΜPD42280
1992
DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD42280
The information in this document is subject to change without notice.
The mark
#
shows major reviced points.
2 M-BIT FIELD BUFFER
Document No. S11274EJ5V1DS00 (5th edition)
Date Published February 1998 N CP(K)
Printed in Japan
The
μ
PD42280 is a high-speed field buffer equipped with a memory of 256K words
×
8bit (262, 224
×
8bit)
configuration. The high-speed and the low power consumption are realized in CMOS dynamic circuit.
The
μ
PD42280 consists of FIFO (First In First Out) configuration, and the write/read operations are possible
asynchronously and simultaneously.
Because it has refresh circuit internally, 1 field delay line and time axis conversion etc. are realized easily.
Therefore it is suitable for YC separation between frames, interpolation between fields, reproduction of freeze
picture and frame synchronizer in the digital TV, VCR systems.
FEATURES
256K words
×
8 bit FIFO configuration
Write/read operations are possible asynchronously and simultaneously
Reset is possible apart from write/read address (real time reset)
Serial read cycle time
: 30 ns/60 ns (MIN.)
Serial read access time
: 25 ns/40 ns (MAX.)
Serial write cycle time
: 30 ns/60 ns (MIN.)
Self refresh function incorporated
Output enable
All I/O TTL compatible
CMOS low power consumption
: (t
RCK
, t
WCK
= 30 ns) I
CC
= 50 mA (TYP.)
28-pin plastic SOP (450 mil)
....
μ
PD42280GU
28-pin plastic ZIP (400 mil)
....
μ
PD42280V
ORDERING INFORMATION
Read cycle time
(ns)
Access time
(ns)
Write cycle time
(ns)
μ
PD42280GU-30
28-pin plastic SOP (450 mil)
30
25
30
μ
PD42280GU-60
28-pin plastic SOP (450 mil)
60
40
60
μ
PD42280V-30
28-pin plastic ZIP (400 mil)
30
25
30
μ
PD42280V-60
28-pin plastic ZIP (400 mil)
60
40
60
Part number
Package
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