參數(shù)資料
型號(hào)： μPD4265165
廠商： NEC Corp.
英文描述： 64 M-Bit Dynamic Ram(64M 動(dòng)態(tài)存儲(chǔ)器)
中文描述： 64 m位動(dòng)態(tài)隨機(jī)存儲(chǔ)器（6400動(dòng)態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 1/48頁(yè)
文件大?。?/td> 535K
代理商： ΜPD4265165
1997
DATA SHEET
MOS INTEGRATED CIRCUIT
μ
PD42S65165, 4265165
Description
The
μ
PD42S65165, 4265165 are 4,194,304 words by 16 bits CMOS dynamic RAMs with optional EDO.
EDO is a kind of the page mode and is useful for the read operation.
Besides, the
μ
PD42S65165 can execute CAS before RAS self refresh.
These are packaged in 50-pin plastic TSOP (II).
Features
EDO (Hyper page mode)
4,194,304 words by 16 bits organization
Single +3.3 V
±
0.3 V power supply
Fast access and cycle time
Part number
Power consumption Access time
Active (MAX.)
R/W cycle time
(MIN.)
EDO (Hyper page mode)
cycle time (MIN.)
(MAX.)
μ
PD42S65165-A50, 4265165-A50
540 mW
50 ns
84 ns
20 ns
μ
PD42S65165-A60, 4265165-A60
468 mW
60 ns
104 ns
25 ns
The
μ
PD42S65165 can execute CAS before RAS self refresh.
Part number
Refresh cycle
Refresh
Power consumption
at standby (MAX.)
μ
PD42S65165
4,096 cycles/128 ms
RAS only refresh, Normal read/write,
CAS before RAS self refresh,
CAS before RAS refresh, Hidden refresh
0.72 mW
(CMOS level input)
μ
PD4265165
4,096 cycles/64 ms
RAS only refresh, Normal read/write,
CAS before RAS refresh, Hidden refresh
1.8 mW
(CMOS level input)
The information in this document is subject to change without notice.
64 M-BIT DYNAMIC RAM
4 M-WORD BY 16-BIT, EDO,
BYTE READ/WRITE MODE
Document No. M12282EJ1V1DS00 (1st edition)
Date Published February 1997 N
Printed in Japan
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