參數(shù)資料
型號(hào)： μPD29F008AL-X
廠商： NEC Corp.
英文描述： 8 M-Bit CMOS Low Voltage Flash Memory(8M CMOS低壓閃存)
中文描述： 8 m位的CMOS低電壓快閃記憶體（800萬(wàn)的CMOS低壓閃存）
文件頁(yè)數(shù)： 10/44頁(yè)
文件大小： 249K
代理商： ΜPD29F008AL-X
Preliminary Data Sheet
10
μ
PD29F008AL-X
3. Bus Operations
The Operation modes of this device are described below.
Table 3-1. Bus Operation
Operation
/CE
/OE
/WE
A9
A6
A1
A0
I/O0 - I/O7
/RESET
Read
L
L
H
Address input
Data output
H
Write
L
H
L
Address input
Data input
H
Standby
H
×
×
×
×
×
×
Hi-Z
H
Output disable
L
H
H
×
×
×
×
Hi-Z
H
Hardware reset
×
×
×
×
×
×
×
Hi-Z
L
Sector protect
L
V
ID
Pulse
V
ID
L
H
L
×
H
Verify sector protect
L
L
H
V
ID
L
H
L
Code
H
Temporary sector unprotect
×
×
×
×
×
×
×
×
V
ID
Read product
Manufacturer code
L
L
H
V
ID
L
L
L
Code
H
ID code
Note
Device code
L
L
H
V
ID
L
L
H
Code
H
Note
The manufacturer code and device code can also be read by using commands. See section
4.3 Read
Product ID Code
.
Remark
H : V
IH
, L : V
IL
,
×
: Don't care, V
ID
: 12.0 V
±
0.5 V
3.1 Read
At power ON or reset (hardware reset or reset command), the device is reset to read mode.
When the device is in read mode, no command is necessary for reading data. Data can be read using the standard
microprocessor read cycle.
The read mode is maintained until the contents of the command register are changed.
3.2 Write
Command write can be done using the standard microprocessor write timing.
The command is written to the command register. The command register has the function to latch the address and
data necessary for executing an instruction, and does not take up memory.
When an incorrect address or data is written, or addresses and data are written in an incorrect sequence, the device
is reset to the read mode.
3.3 Standby
When no write or read is performed, the device can be placed in standby mode. In this mode, the power
consumption is considerably reduced.
The device goes into standby mode when the /CE and /RESET pins are maintained at V
IH
. At this time, the supply
current can be kept at 5
μ
A or below by maintaining the /CE and /RESET at V
CC
±
0.3 V.
3.4 Output Disable
The output of the device can be disabled by maintaining /OE at V
IH
, at which time the output goes into high
impedance.
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