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參數(shù)資料
| 型號： | ZXLD1615ET5 |
| 廠商： | ZETEX PLC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SEE A3240ELT-T |
| 中文描述： | 0.5 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO5 |
| 封裝： | TSOT-23, 5 PIN |
| 文件頁數(shù)： | 4/12頁 |
| 文件大?。?/td> | 180K |
| 代理商： | ZXLD1615ET5 |
Device Description
The device is a PFM flyback dc-dc boost converter,
working in discontinuous mode.
With reference to the chip block diagram and typical
application circuit, the operation of the device is as
follows:
Control loop
When 'EN' is high, the control circuits become active
and the low side of the coil (L1) is switched to ground
via NDMOS transistor (MN). The current in L1 is
allowed to build up to an internally defined level
(nominally 320mA) before MN is turned off. The
energy stored in L1 is then transferred to the output
capacitor (C2) via schottky diode (D1). The output
voltage is sensed at pin 'FB' by external resistors R1
and R2 and compared to a reference voltage V
(1.025V nominal). A comparator senses when the
output voltage is above that set by the reference and
its output is used to control the 'off' time of the
output switch. The control loop is self-oscillating,
producing pulses of up to 5 s maximum duration
(switch 'on'), at a frequency that varies in proportion
to the output current. The feedback loop maintains a
voltage of V
at the FB pin and therefore defines a
maximum output voltage equal to V
*(R1+R2)/R1.
The minimum 'off' time of the output switch is fixed
at 0.5 s nominal, to allow time for the coil's energy
to be dissipated before the switch is turned on again.
This maintains stable and efficient operation in
discontinuous mode.
Filtered PWM operation
The input of an internal low pass filter is switched to
V
when the EN pin is high and switched to ground
when the EN pin is low. The output of this filter
drives the comparator within the control loop. A
continuous high state on EN therefore provides a
filtered voltage of value Vref to the comparator.
However, by varying the duty cycle of the EN signal
at a suitably high frequency (f>10kHz), the control
loop will see a voltage, that has an average value
equal to the duty cycle multiplied by V
. This
provides a means of adjusting the output voltage to a
lower value. It also allows the device to be both
turned on and adjusted with a single signal at the
‘EN’ pin. The output during this mode of operation
will be a dc voltage equal to V
REF
*(R1+R2)/R1 x duty
cycle.
Gated PWM operation
The internal circuitry of the ZXLD1615 is turned off
when no signal is present on the 'EN' pin for more
than 120 s (nominal). A low frequency signal applied
to the EN pin will therefore gate the device 'on' and
'off' at the gating frequency and the duty cycle of this
signal can be varied to provide an average output
equal to V
*(R1+R2)/R1 x duty cycle. For best
accuracy, the gating frequency should be made as
low as possible (e.g. below 1kHz), such that the turn
off delay of the chip is only a small proportion of the
gating period
Further details of setting output current are given in
the application notes.
ZXLD1615
S E M IC O N D U C T O R S
ISSUE 3 - AUGUST 2004
4
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