參數(shù)資料
型號(hào): ZXLD1601
廠商: Zetex Semiconductor
英文描述: ADJUSTABLE DC - DC BOOST CONVERTER WITH INTERNAL SWITCH IN SC70
中文描述: 可調(diào)式直流-直流升壓轉(zhuǎn)換器內(nèi)部采用SC70開關(guān)
文件頁(yè)數(shù): 5/12頁(yè)
文件大?。?/td> 134K
代理商: ZXLD1601
Device Description
The device is a PFM flyback dc-dc boost converter,
working in discontinuous mode.
With reference to the chip block diagram and typical
application circuit, the operation of the device is as
follows:
Control loop
When ‘EN’ is high, the control circuits become active
and the low side of the coil (L1) is switched to ground
via NDMOS transistor (MN). The current in L1 is
allowed to build up to an internally defined level
(nominally 320mA) beforeMN is turnedoff.Theenergy
stored in L1 is then transferred to the output capacitor
(C2) via Schottky diode (D1). The output voltage is
sensed at pin ‘V
’ by internal resistors R1 and R2
(which may be shunted externally at pin ‘FB’) and
compared to a reference voltage V
(1.025V
nominal). A comparator senses when the output
voltage is above thatsetby the reference and its output
is used to controlthe‘off’ timeoftheoutputswitch.The
control loop is self-oscillating, producing pulses of up
to 5
μ
s maximum duration (switch ‘on’), at a frequency
that varies in proportion to the output current. The
feedbackloop maintains a voltageofVREF attheFB pin
andthereforedefines amaximum outputvoltageequal
to V
REF
*(R1+R2)/R1. The minimum ‘off’ time of the
output switch is fixed at 0.5
μ
s nominal, to allow time
for the coil’s energy to be dissipated before the switch
is turned on again. This maintains stable and efficient
operation in discontinuous mode.
Filtered PWM operation
The input of an internal low pass filter is switched to
V
when the EN pin is high and switched to ground
when the EN pin is low. The output of this filter drives
the comparator within the control loop. A continuous
highstateonEN thereforeprovides a filtered voltageof
value Vref to the comparator. However, by varying the
duty cycle of the EN signal at a suitably high frequency
(f>10kHz), the control loop will see a voltage, that has
an average value equal to the duty cycle multiplied by
V
. This provides a means of adjusting the output
voltage to a lower value. It also allows the device to be
both turned on and adjusted with a single signal at the
‘EN’ pin. The output during this mode of operation will
beadc voltageequalto V
REF
*(R1+R2)/R1x duty cycle.
Gated PWM operation
The internal circuitry of the ZXLD1601 is turned off
when no signal is present on the ‘EN’ pin formore than
120
μ
s (nominal). A low frequency signal applied to the
EN pin will therefore gate the device ‘on’ and ‘off’ atthe
gating frequency and the duty cycle of this signal can
be varied to provide an average output equal to V
*(R1+R2)/R1 x duty cycle. For best accuracy, the gating
frequency should be made as low as possible (e.g.
below 1kHz), such that the turn off delay of the chip is
only a small proportion of the gating period
Furtherdetails ofsetting outputcurrentare given in the
application notes.
ZXLD1601
S E M IC O N D U C T O R S
ISSUE 3 - AUGUST 2004
5
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