參數(shù)資料
型號: ZXFV4089
廠商: Zetex Semiconductor
元件分類: 運動控制電子
英文描述: VIDEO AMPLIFIER WITH DC RESTORATION
中文描述: 視頻放大器直流修復(fù)
文件頁數(shù): 4/5頁
文件大?。?/td> 53K
代理商: ZXFV4089
ZXFV4089DETAILED OPERATING NOTES
Introduction
This device provides a video feed-back amplifier
together with a sample-hold system to allow DC
restoration. The Connection Diagram on page 1shows
a typical video signal application.
termination is shown in the diagram, but if desired the
output can drive a 75 ohm cable via a 75 ohm series
terminating resistor.
Amplifier configuration
The amplifier configuration uses high gain with
feedback in a non-inverting configuration.
external resistors are required to set the gain.
restorationvoltageis setby anexternalreference, Vref,
normally ground. The input signal is applied via an
externalinputcoupling capacitorwhich is used to store
a DC control level when the sample-hold switch is
open. When the switch is closed, the stored level is
driven to a new value by an external sampling pulse.
DC restoration
HOLD is a TTL input signal which is buffered and
controls the sample-hold switch. A logic LOW state
closes the switch and so enables the feedback control
loop to set the output level equal to Vref (usually
ground). The level of DC shift is maintained when the
logic control returns to the HIGH state and the switch
opens. Inthis way thewholewaveform is conditionally
level shifted, or ‘restored’ to the new DC level.
No output
Two
The
The sample-hold loop contains the video feed-back
amplifier within its path, and also includes an
additional sample-hold sense amplifier which
compares Vref with the output voltage using an
internal low-pass filter. In the high state, the switch is
open and the average DC level remains fixed apart
from a small drift due to the input bias current of the
amplifier and switch leakage (see below).
Video function
In the video application, the HOLD input state will be
HIGH during the picture line sweep and a
negative-going sampling pulse of typically 1.2 μs
duration will be applied during a central portion of the
Back Porch interval, so that the Back Porch or ‘Black’
level is clamped to ground. For each line scan, this
gives a brightness level consistent with that of the
original camera signal, despite the AC coupling.
The value of the coupling capacitor affects two main
characteristics of the circuit.
charging current, together with the capacitor value,
determines the maximum DC voltage correction which
can be applied at each sample. For a charging current
limit of 300 μA applied for 2 μs, the charge injected is
Firstly, the available
Qmax = 300 μA x 1.2 μs = 360 pC.
Then the maximum voltage shift correction is
Vmax = Qmax/C = 360 pC / 0.01 μF
= 36 mV.
Secondly, in the hold state, the voltage drift is affected
as described below.
Sample-hold drift
In the HOLD state, the drift rate is equal to the
bias/leakage current of about 1 μA divided by the
coupling capacitor value. For a value of 0.01 μF, the
drift rate is then 100 μV/μs. For the typical video line
scan, the switch remains open for the rest of the scan
duration, or about 62 μs. The drift at the end of the line
scan has therefore accumulated to about 6.2 mV. This
will be acceptable for most applications, but if desired
it can be reduced by increasing the value of the
coupling capacitor. This will resultin a proportionately
smaller value of the maximum available correction
voltage at each scan as described above. Normally,
once settled, the video system requires only a very
small correction at each scan, so this will not present
any problem.
Supply filtering & printed circuit layout
In the applied circuit, the power filtering and printed
layout design needs special attention as is appropriate
for a high-speed analog circuit. For each supply lead,
use a leadless ceramic chip capacitorplaced very close
to the device power pin.
recommended. In addition, a larger value capacitor,
which should be ceramic or solid tantalum
construction, with a value of 1 to 10 μF, is also
recommended for connection to each supply fairly
close to the device.
A value of 0.1μF is
The
interconnections on the component side (top copper
layer) and a continuous ground plane should be
provided on another layer with plated via holes
providing low inductance ground connections for the
device and other components.
frequency response is affected to some extent by stray
capacitance at the inverting input at pin 1. This effect
can be minimised by providing a small cut-out area in
theground planeand otherlayers around pin1, though
this may not always be necessary for the application.
layout
naturally
requires
some
short
The amplifier
ZXFV4089
ADVANCED INFORMATION ISSUE D - SEPTEMBER 2002
4
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