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參數(shù)資料
| 型號： | ZXFV401N16TC |
| 廠商： | ZETEX PLC |
| 元件分類： | 信號分離 |
| 英文描述： | SYNC SEPARATOR WITH VARIABLE FILTER |
| 中文描述： | SYNC SEPARATOR IC, PDSO16 |
| 封裝： | SO-16 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大小： | 117K |
| 代理商： | ZXFV401N16TC |
ZXFV401
PROVISIONAL ISSUE A - FEBRUARY 2002
4
PIN No.
PIN NAME
TYPE
FUNCTION
1
RFILT
Resistor
control
Controls the input colour carrier filter characteristic.
resistor R
FILT
connected from this pin to 0V sets the bandwidth.
Smaller R
FILT
gives increased bandwidth. See the detailed operating
description below.
An external
2
RNOSIG
Resistor
control
Controls the no-signal detector level.
connected from this pin to 0V sets the thrAn external resistor R
to the equation
V
PMIN
= 0.75 R
NOSIG
/ R
SET
where V
PMIN
is the minimum detected sync pulse amplitude at pin 4
and R
SET
is the resistor value at pin 12.
Composite sync logic output. Includes all sync pulses derived from the
input video.
Input to colour carrier filter.
This is the main analog (unfiltered)
composite video input used when colour carrier filtering is required. A
voltage clamp circuit and adaptive current source are also included at
this node. See the detailed operating description.
Vertical sync output. This is an active low pulse commencing on the first
vertical sync pulse trailing (rising) edge and ending near the second
next equalising pulse. See timing diagram.
Provides ground return path for internal logic output buffer circuits.
Normally connected externally to a common PCB ground plane.
Analog outnominally 2. This output is normally capacitor-coupled to pin 8.
Input for filtered analog video signal input. This is the direct input to the
sample/hold and sync slicing comparator providing the logic timing
edges. This input is normally coupled via an external capacitor from
FILTOUT, pin 7. It may be used as the signal input where the colour
carrier filter is not required. Includes a clamp similar that of pin 4.
Analog outpeak sync pulse amplitude if the filter is used.
Logic output, which goes high after a time-out delay when no signal is
present. The threshold level is controlled at pin 2.
Burst or Back Porch logic output, an active low monostable pulse
triggered from rising composite sync pulse edges. The width is set by
R
to overlap most of the steady part of the back porch, assuming the
colour carrier burst has been attenuated sufficiently by filtering. This
pulse is then suitable for controlling an external black level clamping
circuit. See the timing diagram.
Controls the timing interval of the sample/hold circuit and the
monostable interval for the sync outputs according to the application.
An external resistor, R
connected from this pin to 0V establishes the
timing parameter, to which these times are scaled together. See the
detailed operating description.
Odd field logic output. High during an odd numbered field, low during
even. This output is timed with the start of the VSYNC pulse.
Power in
Power supply input, +5V.
NOSIG
3
CSYNC
Logic out
4
FILTIN
Analog in
5
VAYNC
Logic out
6
OVD
Ground
7
FILTOUT
8
FVIDIN
Analog in
9
VLEV
10
NOSIG
Logic out
11
BKPCH
Logic out
12
RSET
Resistor
control
13
ODDFLD
Logic out
14
V+
15
HSYNC
Logic out
Horizontal sync logic output. Monostable output derived from CSYNC
falling edges, it achieves a steady stream of 5μs pulses. The half line
events during the field blanking interval are eliminated. See timing
diagram.
Analog ground.
Normally connected externally to a common PCB
ground plane.
16
OVA
Ground
CONNECTIONS
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