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參數(shù)資料
| 型號： | ZR36060 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:19; Series:; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:14; Circular Contact Gender:Socket; Circular Shell Style:Cable Receptacle; Insert Arrangement:14-19 |
| 中文描述： | 綜合JPEG編解碼器 |
| 文件頁數(shù)： | 5/46頁 |
| 文件大小： | 307K |
| 代理商： | ZR36060 |
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3
Integrated JPEG CODEC
1.0 INTRODUCTION
1.1 The ZR36060
The ZR36060 is an integrated JPEG codec targeted to video
capture and editing applications in desktop and laptop comput-
ers. Figure 1 shows an example of a typical application, a video
editing subsystem for PCI bus computers.
The ZR36060 integrates the functionality of a JPEG codec such
as the ZR36050, a raster-to-block converter such as the
ZR36015, as well as the strip buffer SRAM for the raster-to-block
converter and additional functions. It is based on the field
proven, fully compliant Zoran JPEG device technology, and
incorporates Zoran’s patented bit rate control mechanism.
In compression, the ZR36060 accepts YUV 4:2:2 digital video,
performs optional cropping and decimation, and encodes it into
a JPEG baseline compressed bitstream, which it outputs to a
host controller. In decompression, it receives the bitstream from
the host controller, decodes it back to YUV 4:2:2 format digital
video, up-scales it if required, and outputs the video to a com-
posite video encoder or other destination.
The ZR36060 incorporates hardware support for multiplexing
two video sources (in rectangular windows) in compression, or
the reconstructed video with another source in decompression.
It can operate as a video sync master or slave, with 8-bit or 16-
bit video bus widths. A pixel flow control mechanism is provided
for convenient implementation of non-real-time video rates, such
as for still picture compression.
The code interface of the ZR36060 can operate in 8-bit master,
8-bit slave or 16-bit slave modes. In slave mode, code transfer
shares the host interface, which is generic enough to be able to
interface gluelessly with a variety of host controllers, ranging
from the dedicated, high performance ZR36057 to common
microcontrollers.
The ZR36060 is a CMOS device, requiring a 3.3 Volt power
supply. Its inputs and outputs are 5 Volt tolerant. A power-down
(“sleep”) mode reduces current consumption to a very low level,
while preserving the logic state of the device.
A block diagram of the ZR36060 is shown in Figure 2.
1.2 The ZR36060 and the JPEG Standard
The JPEG standard, ISO/IEC 10918-1, defines a whole range of
options for compressing continuous-tone images - a baseline
lossy compression process, extended lossy processes, lossless
compression, and hierarchical compression methods. The
ZR36060 implements the baseline process.
Even the baseline method is defined by the JPEG standard to
provide maximal flexibility in choosing the color space in which
an image is compressed - an image can have an almost unlimit-
ed number of color components, and these can be compressed
in a single scan, or in multiple scans. Because its main targeted
application is motion color video compression and decompres-
sion, the architecture of the ZR36060 supports one particular
subset: Since the ZR36060 supports only the YUV 4:2:2 pixel
format, it supports three color components, in a single inter-
leaved scan.
1.2.1 JPEG baseline overview
The JPEG baseline compression method is based on the
discrete cosine transform or DCT. The DCT is performed on 8x8
blocks of samples, of each color component, resulting in a set of
64 DCT coefficients for each block. Thus, in order for a normal
raster-scanned image to be compressed, it must first be convert-
ed to block format This requires that an 8-line strip of the image
(containing 8 lines of each color component) be stored in a strip
buffer, so that the samples can be re-ordered (see Figure 2).
For subsequent stages of the compression, the 64 DCT coeffi-
cients of each block are further re-ordered by scanning the block
in a zig-zag sequence. Each of the 64 coefficients is quantized
using the appropriate value from a 64-entry quantization table. In
the ZR36060, it is possible to define three different quantization
tables, one per color component; generally, however, two tables
are used, one for the luminance component and one for the
chrominance component.
The quantized DCT coefficients are passed to a Huffman
encoder, for the final stage of the process. The Huffman coding
is performed separately for the DC coefficient of each block (the
first coefficient of the block), and the remaining 63 AC coeffi-
Video Interface
Figure 2. ZR36060 Block Diagram
VSYNC
HSYNC
FI
BLANK
PVALID
SUBIMG
POE
Y[7:0]
UV[7:0]
Strip Memory
JPEG CODEC
RTBSY
DATERR
CODE FIFO
(512 x 8 bits)
Internal
Configuration
Memory
(1K x 8 bits)
(Registers,
Markers, Tables)
Control
START
FRAME
END
EOI
COMP
SLEEP
RESET
PLL & Clocks
VCLK
VCLKx2
CODE [7:0]
CCS
COE
CWE
CBUSY
ADDR[1:0]
JIRQ
ACK
CS
WR
RD
CODE and Host Interface
DATA[7:0]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZR36060PQC | Integrated JPEG CODEC |
| ZR36067 | AV PCI CONTROLLER |
| ZR36067PQC | AV PCI CONTROLLER |
| ZR36067 | PCI Adapter Intended for Multimedia Applications on PCI Systems(PCI（外圍部件互連）適配器（用于PCI系統(tǒng)的多媒體）) |
| ZR36215 | SupraAV SVCD Decoder(SupraAV 超級VCD解碼器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZR36060PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Integrated JPEG CODEC |
| ZR36060PQC-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36060PQC-29.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| ZR36067 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
| ZR36067PQC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:AV PCI CONTROLLER |
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