參數資料
型號: ZR36016PQC-30
廠商: Electronic Theatre Controls, Inc.
英文描述: INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER
中文描述: 多功能彩色空間/光柵逐戶轉爐
文件頁數: 21/36頁
文件大?。?/td> 242K
代理商: ZR36016PQC-30
21
Integrated Color Space / Raster-To-Block Converter
Limitations on the value of PAX are given in Table 18.
The limitations on PAY when RSTR = 0 are in Table 19.
In the case of RSTR = 1, the maximum value of PAY is 65536 in
any format. The minimum value is 1 when VERT = 0 and is 2
when VERT = 1.
ZR36050 Bus Interface
The ZR36016 connects directly with the ZR36050 as shown in
Figure 30. The data transfer rate on BDATA(7:0) is always at the
SYSCLK clock rate regardless of the format.
The direction of the bidirectional pins on the ZR36016, and
therefore possible transfers, is determined by the COMP input
signal from the ZR36050 rather than the CMPR bit of the Mode
Table 18: Limitations on PAX
RSTR
Bit
HORZ
PAX
ZR36050
1:0:0
4:2:2
4:1:1
(H2V2)
4:1:1
(H4V1)
4:4:4
4:4:4:4
0
0
Max Value
8192
4096
2720
5440
2728
2048
Min Value
8
16
16
32
8
8
Multiple of…
8
16
16
32
8
8
1
Max Value
16348
8192
8192
5456
4096
Min Value
16
32
32
16
16
Multiple of…
16
32
32
16
16
1
0
Max Value
65536
32768
43688
21840
16348
Min Value
8
8
8
8
8
Multiple of…
8
8
8
8
8
1
Max Value
65536
65536
65536
43688
32768
Min Value
16
16
16
16
16
Multiple of…
16
16
16
16
16
Table 19: Limitations on PAY
VERT Bit
PAY
ZR36050
1:0:0
4:2:2
4:1:1
(H2V2)
4:1:1
(H4V1)
4:4:4
4:4:4:4
0
Max Value
65536
65536
65536
65536
65536
65536
Min Value
8
8
16
8
8
8
Multiple of…
8
8
16
8
8
8
1
Max Value
65536
65536
65536
65536
65536
Min Value
16
16
16
16
16
Multiple of…
16
16
16
16
16
Figure 30. ZR36016 to ZR36050 Connections
ZR36016
ZR36050
DSYNC
EOS
STOP
BDATA[7:0]
COMP
DCLK
DSYNC
EOS
STOP
BDATA[7:0]
COMP
SYSCLK
System Clock
register in the ZR36016. These two conditions are shown in
Table 20.
If the ZR36016 is set for compression in the Mode register and
receives a low input on COMP indicating expansion it will output
an active STOP provided it is not already processing.
For transfers with the ZR36050 the DSYNC signal is treated as
a pixel enable when RSTR = 1 for raster-to-raster transfers
rather than as a block enable for block transfers. See the
ZR36050 User’s Manual for its timing information.
JPEG MCU (Minimum Coded Unit) Structure
Data transfer between the ZR36016 and the ZR36050 is always
in units of the MCU. The structure of the MCU for each of the
supported compressed data formats is shown in Table 21. For
baseline compression, the entities of the MCU are 8x8 blocks;
for lossless and fast preview, they are individual samples.
Table 20: Directional Status of ZR36016 Pins on the
ZR36050 Interface
Pin
Compression
Expansion
COMP
IN High
IN Low
DSYNC
OUT
INT
EOS
OUT
IN
STOP
IN
OUT
BDATA(7:0)
OUT
IN
Table 21: MCU Structure
ZR36050
Image Format
MCU Structure
4:2:2
Y0, Y1, Cb0, Cr0
4:1:1 (H4V1)
Y0, Y1, Y2, Y3, Cb0, Cr0
4:1:1 (H2V2)
Y0, Y1, Y2, Y3, Cb0, Cr0
4:4:4
R0, G0, B0
4:4:4:4
C0, M0, Y0, K0
4:0:0
Y0
Y0
Y1
Cb0 Cr0
Y0
Y1
Cb0 Cr0
Y2
Y3
Y0
Y2
Y1
Y3
Cb0 Cr0
R0
G0
B0
C0
M0
Y0
K0
Y0
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