參數(shù)資料
型號: ZR36016
廠商: Electronic Theatre Controls, Inc.
英文描述: INTEGRATED COLOR SPACE / RASTER-TO-BLOCK CONVERTER
中文描述: 多功能彩色空間/光柵逐戶轉(zhuǎn)爐
文件頁數(shù): 15/36頁
文件大?。?/td> 242K
代理商: ZR36016
15
Integrated Color Space / Raster-To-Block Converter
1.
N
= Decimation/Interpolation is performed on these components; – = Not performed or not applicable.
Table 15: Decimation And Interpolation
ZR36050 Image
Format
HORZ
VERT
Compression Format and
Resolution
Minimum
Value
PXCLK to SYSCLK
Frequency Ratio
Bit
Decimation/
Interpolation
[1]
PAX
PAY
CKRT
Y
CB/CR
0
1
4:2:2
1
N
N
1
2:1:1 (Quarter Screen)
32
16
1/2
1
4:2:2
1
N
N
0
2:1:1 (Horizontal Half-Screen)
32
8
1/2
1
4:2:2
0
1
4:2:2 (Vertical Half-Screen)
16
16
1/2
4:2:2
0
0
4:2:2 (Full-Screen)
16
8
1/2
4:1:1 (H4V1)
1
N
1
2:1:1 (Quarter Screen)
32
16
1/2
1
4:1:1 (H4V1)
1
N
0
2:1:1 (Horizontal Half-Screen)
32
8
1/2
1
4:1:1 (H4V1)
0
1
4:1:1 (Vertical Half-Screen)
32
16
1/2
4:1:1 (H4V1)
0
0
4:1:1 (Full-Screen)
32
8
1/2
4:1:1 (H2V2)
4:1:1 (Full-Screen)
16
16
1/2
4:4:4
1
Each Component
1
2:2:2 (Quarter Screen)
16
16
1/4
1/2
4:4:4
1
Each Component
0
2:2:2 (Horizontal Half-Screen)
16
8
1/4
1/2
4:4:4
0
1
4:4:4 (Vertical Half-Screen)
8
16
1/4
4:4:4
0
0
4:4:4 (Full-Screen)
8
8
1/4
4:4:4:4
1
Each Component
1
2:2:2:2 (Quarter Screen)
16
16
1/2
1
4:4:4:4
1
Each Component
0
2:2:2:2 (Horizontal Half-Screen)
16
8
1/2
1
4:4:4:4
0
1
4:4:4:4 (Vertical Half-Screen)
8
16
1/2
4:4:4:4
0
0
4:4:4:4 (Full-Screen)
8
8
1/2
4:0:0 (1:0:0)
1
N
1
2:0:0 (Quarter Screen)
16
16
1
4:0:0 (1:0:0)
1
N
0
2:0:0 (Horizontal Half-Screen)
16
8
1
4:0:0 (1:0:0)
0
1
4:0:0 (Vertical Half-Screen)
8
16
1
4:0:0 (1:0:0)
0
0
4:0:0 (Full-Screen)
8
8
1
Table 16 shows with shaded boxes which samples are dropped
or reconstructed respectively by the horizontal decimation or
interpolation process, for the various formats when HORZ = 1.
When filtering is selected with the HRFL bit, the value at time n
is [Y(n-1) + 2Y(n) + Y(n+1)]/4 on compression and is [Y(n-1) +
Y(n+1]/2 on expansion. When n is at the edge of a window, Y(n)
is copied and used for Y(n-1) or Y(n+1) as appropriate.
Table 16: The Horizontal Decimation/Interpolation
4:0:0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
4:4:4
R
R
R
R
R
R
R
R
G
G
G
G
G
G
G
G
B
B
B
B
B
B
B
B
4:4:4:4
Y
C
Y
C
Y
C
Y
C
M
K
M
K
M
K
M
K
4:2:2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Cb6
Cr6
4:1:1
(H4V1)
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Cb0/Cr0
Cb4/Cr4
Figure 12 illustrates a typical case of data flow, from the PXIN
bus at the top through to the strip buffer, for an RGB input with
color space conversion to YCbCr and horizontal decimation,
with CKRT=1.
In this example, the internal pipeline delays of the various pro-
cessing stages are ignored. The example is also intended to
clarify the SYSCLK to PXCLK relationship. The strip buffer is
always operated at a rate of half the SYSCLK frequency. When
horizontal decimation is performed and CKRT=1, as in the
above example, the PXCLK rate (and the PXIN pixel rate) is the
same as that of SYSCLK. If horizontal decimation had not been
selected, or if CKRT=0, the PXCLK rate would have been half
the SYSCLK rate, the same as the strip buffer access rate.
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