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| 型號(hào)： | ZPSD602(V)E1 |
| 英文描述： | Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個(gè)可編程I/O,通用PLD有63個(gè)輸入) |
| 中文描述： | 現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備和嵌入式微-細(xì)胞（可編程邏輯，零功耗，4K的位的SRAM，26余個(gè)可編程輸入/輸出，通用PLD的有63個(gè)輸入） |
| 文件頁(yè)數(shù)： | 49/98頁(yè) |
| 文件大小： | 484K |
| 代理商： | ZPSD602(V)E1 |
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ZPSD6XX(V) Family
12-49
I/O Ports
(cont.)
Microcontroller
Port A (3:0)
Port A (7:4)
Port B (3:0)
Port B (7:4)
8051XA (8-Bit)
N/A*
Address (7:4)
Address (11:8)
80C251
(Page Mode)
N/A
N/A
Address (11:8)
Address (15:12)
All Other 8-Bit
Multiplexed
Address (3:0)
Address (7:4)
Address (3:0)
Address (7:4)
8051XA (16-Bit)
N/A
Address (7:4)
Address (11:8)
Address (15:12)
All Other 16-Bit
Multiplexed
Address (3:0)
Address (7:4)
Address (11:8)
Address (15:12)
8-Bit
Non-Multiplexed Bus
N/A
N/A
Address (3:0)
Address (7:4)
Table 28. I/O Port Latched Address Output Assignments
Port A and B – Functionality and Structure
Port A and B have similar functionality and structure as shown in Figure 23. The two ports
can be configured to perform one or more of the following functions:
J
MCU I/O Mode
J
GPLD Output – Micro
Cells McellAB[7:4] can be connected to Port A PA[7:4}
or Port B PB[7:4].
J
ECSPLD Output – External chip select output can be connected to either Port A
PA[3:0] or Port PB[3:0].
J
Latched Address output – Provide latched address output per Table 28.
J
Address In – Additional high address inputs using the Input Micro
Cells.
J
Open Drain/Slew Rate – pins PA[3:0] and PB[3:0] can be configured to Open Drain Mode
pins PA[7:4] and PB[7:4] can be configured to fast slew rate
J
Data Port – Port A to D[7:0} for 8 bit non-multiplexed bus
Port B to D[15:8] for 16-bit non-multiplexed bus
J
Peripheral Mode – Port A only
N/A = Not Applicable.
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