參數(shù)資料
型號(hào)： ZPSD512B1V-C-20U
廠商： 意法半導(dǎo)體
英文描述： Low Cost Field Programmable Microcontroller Peripherals
中文描述： 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備
文件頁數(shù)： 14/153頁
文件大?。?/td> 1036K
代理商： ZPSD512B1V-C-20U
PSD5XX Famly
11
9.0
The PSD5XX
Architecture
PSD5XX consists of seven major functional blocks:
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ZPLDBlocks
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Bus Interface
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I/OPorts
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Memory Block
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Power Management Unit
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Counter/Timer
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Interrupt Controller
The functions of each block are described in the following sections. Many of the blocks
perform multiple functions, and are user configurable. The chip configurations are specified
by the user in the PSDsoft Development Software; some are specified by setting up the
appropriate bits in the configuration registers during run time.
9.1 ZPLDBlock
Key Features
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3 Embedded ZPLD devices
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Maximum 30 macrocells
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Combinatorial/registered outputs
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Maximum 140 product terms
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Programmable output polarity
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User configured register clear/preset
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User configured register clock input
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61 Inputs
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Accessible via 24 I/O pins
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Power Saving Mode
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UV-Erasable
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Generate user defined interrupts to Interrupt Controller
and controls to Counter/Timer
General Description
The ZPLD block has 3 embedded PLD devices:
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DPLD
The Address Decoding PLD, generating select signals to internal I/O or memory blocks.
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GPLD
The General Purpose PLD provides 24 programmable macrocells for general or
complex logic implementation; dedicated to user application.
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PPLD
The Peripheral PLD, includes 6 programmable macrocells. The PPLD provides control
to the operation of the Counter/Timer and Interrupt Controller.
Figure 4 shows the architecture of the ZPLD. The PLD devices all share the same
input bus. The true or complement of the 61 input signals are fed to the programmable
AND-ARRAY. Names and source of the input signals are shown in Table 3. The PA, PB, PE
signals, depending on user configuration, can either be macrocell feedbacks or inputs from
Port A, B or E.
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