PSD5XX Famly
107
System
Configuration
(Cont.)
Register Name
Register Function
PAGE REGISTER
A 4-bit register that supports paging.
INTR. READ
CLEAR
Reading this register clears all the pending edge sensitive
interrupts.
INTR.
EDGE/LEVEL
Define interrupt input as level or edge sensitive.
INTR. MASK
Mask selected interrupt input.
INTR.
REQUEST LATCH
A
“
1
”
in the register indicates the corresponding interrupt is
pending.
INTR.
PRIORITY STATUS
The register indicates which pending interrupt has the highest
priority.
1. Configures the PSD SRAM to be accessed by
“
PSEN
”
as
program space (8031 design).
2. Enable the Peripheral I/O Mode of Port A.
VM
PMMR0
PMMR1
Power management registers; enable the PSD Power Down Mode
and other power saving configurations.
STATUS FLAGS
Counter/Timer Freeze Acknowledge bits.
GLOBAL
COMMAND
Specifies the Counter/Timer operation mode; and to start or stop
the Counter/Timers.
DLCY
Specifies the delay cycles to the Counter/Timers.
SOFTWARE
LOAD/STORE
This register enables a load (to the Counter/Timer) or store
(in the Image Register) operation.
FREEZE
COMMAND
This register disables the timer state-machine before access to the
Image Register is allowed.
CMD3 – 0
Command Registers for the configuration of the Counter/Timers.
CNTR3 – 0
The four 16-bit Counter/Timers.
IMG3 – 0
The Image Registers for CNTR3 – 0.
Table 33. Oher Register Function