參數(shù)資料
型號(hào)： ZPSD512B0-C-90JI
廠商： 意法半導(dǎo)體
英文描述： Slide Switch; Circuitry:DPDT; Contact Current Max:4A; Switch Operation:On-Off-On; Switch Terminals:Solder Lug; Leaded Process Compatible:Yes; Mounting Type:PCB RoHS Compliant: Yes
中文描述： 低成本現(xiàn)場可編程微控制器外圍設(shè)備
文件頁數(shù)： 65/153頁
文件大?。?/td> 1036K
代理商： ZPSD512B0-C-90JI
PSD5XX Famly
62
Power
Management
Unit
(Cont.)
Port Configuration
Pin Status
I/O Port
Unchanged
ZPLD Output
Depend on Inputs to the ZPLD
Address Out
Undefined
Data Port
Tri-stated
Special Function Out
Depending on Status of Clock Input
Peripheral I/O
Tri-stated
Table 20. I/OPin Status During Power Down And Sleep Mode
J
Input Clock
The PSD5XX provides the option to turn off the clock inputs to save AC power
consumption. The clock input (CLKIN) is used as a source for driving the following
modules:
J
ZPLD Array Clock Input
J
ZPLD MacroCell Clock Flip Flop
J
APD Counter Clock
J
Counter/Timers Clock
During power down or if any of the modules are not being used the clock to these
modules should be disabled. To reduce AC power consumption, it is especially important
to disable the clock input to the ZPLDS array if it is not used as part of a logic equation.
The ZPLD Array Clock can be disabled by setting PMMR0 bit 5 (ZPLD ACLK). The ZPLD
MacroCell Clock Input can be disabled by setting PMMR0 bit 6 (ZPLD RCLK). The Timer
Clock can be disabled by setting PMMR0 bit 7 (TMR CLK). The APD Counter Clock
will be disabled automatically if Power Down or Sleep Mode is entered through the APD
unit. The input buffer of the CLKIN input will be disabled if bits 5 – 7 PMMR0 are set and
the APD has overflowed.
The Counter/Timers can operate in Sleep Mode if the TMR CLK bit is low, but the power
consumption will be based on the frequency of operation (CLKIN frequency).
NOTES: 1. Power Down does not affect the operation of the ZPLD. The ZPLD operation in this mode is based
only on the ZPLD_Turbo Bit.
2. In Sleep Mode any input to the ZPLD will have a propagation delay of t
LVDV2
.
3. PLD recovery time to normal operation after exiting Sleep Mode. An input to the ZPLD during the
transition will have a propagation delay time of t
LVDV3
.
PLD
PLD
Access
Time
Access
Recovery
Time To
Normal
Access
Propagation
Delay
Recovery
Time To
Normal
Operation
Power Down
Normal t
PD
(Note 1)
0
No Access
t
LVDV
Sleep
t
LVDV2
(Note 2)
t
LVDV3
(Note 3)
No Access
t
LVDV1
Summary of PSD5XX Timng and Standby Current During Power Down
and Sleep Modes
相關(guān)PDF資料
PDF描述
ZPSD512B0-C-90UI ROCKER SWITCH, SPST, ILLUM RED; Switch function type:SPST; Current, contact AC max:16A; Temp, op. max:85(degree C); Width, panel cutout:34.5mm; Length, panel cut-out:23.5mm; Colour:Red (illuminated); Current, contact @ contact RoHS Compliant: Yes
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