參數(shù)資料
型號(hào): ZPSD512B0-C-70U
廠商: 意法半導(dǎo)體
英文描述: Slide Switch; Circuitry:DPDT; Contact Current Max:4A; Switch Operation:On-On; Switch Terminals:Through Hole; Leaded Process Compatible:Yes; Mounting Type:PCB RoHS Compliant: Yes
中文描述: 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備
文件頁數(shù): 12/153頁
文件大?。?/td> 1036K
代理商: ZPSD512B0-C-70U
PSD5XX Famly
9
8.0
Table 2.
PSD5XX Pin
Descriptions
Pin Name
Pin Function
Type
Function Descriptions
ADIO0 – ADIO15
Address/ data bus
I/O
1. Address/data bus, multiplexed
bus mode
2. Address bus, non-multiplexed
bus mode
Multiple functions
1. Read signal
2. E signal (Clock)
3. Data strobe signal
4. Low byte data strobe
RD
Multiple Names
1. Read
2. E
3. DS
4. LDS
I
WR
Multiple Names
1. WR
2. R/W
3. WRL
I
Multiple functions
1. Write signal
2. Read-write signal
3. Low byte write signal
CSI
Chip Select Input
I
Active low, select PSD5XX.
standby mode if high.
RESET
Reset Input
I
Reset I/O ports, ZPLD/macrocells,
Timers and Configuration
Registers. Active low.
CLKIN
Input clock
I
Clock input to Timers, ZPLD
macrocells, ZPLD array, and APD
counter; connect to ground if clock
input not used.
PA0 – PA7
I/O Port A
I/O
Multiple functions
1. I/O port
2. ZPLD/macrocell I/O port
3. Latched address outputs
(PA0–PA7)
(A0–A7)
4. High address inputs (A16 – A23)
5. Timer outputs (PA0 – PA3)
PB0 – PB7
I/O Port B
I/O
Multiple functions
1. I/O port
2. ZPLD/macrocell I/O port
3. Latched address outputs
(PB0–PB7)
(A0–A7) or (A8–A15)
4. Timer outputs (PB0-PB3)
PC0 – PC7
I/O Port C
I/O
Multiple functions
1. I/O port
2. ZPLD input port
3. Latched address outputs
(PC0 – PC7)
(A0–A7)
4. Data Port (D0 – D7,
non-multiplexed bus)
CMOS
or
OD
PD0 – PD7
I/O Port D
I/O
Multiple functions
1. I/O port
2. ZPLD input port
3. Latched address outputs
(PD0–PD7)
(A0–A7) or (A8–A15)
4. Data Port (D8-D15,
non-multiplexed bus)
CMOS
or
OD
The following table describes the pin names and pin functions of the PSD5XX. Pins that
have multiple names and/or functions are defined by user configuration.
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