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參數(shù)資料
| 型號(hào)： | ZPSD511B1V-C-20JI |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Low Cost Field Programmable Microcontroller Peripherals |
| 中文描述： | 低成本現(xiàn)場(chǎng)可編程微控制器外圍設(shè)備 |
| 文件頁(yè)數(shù)： | 51/153頁(yè) |
| 文件大?。?/td> | 1036K |
| 代理商： | ZPSD511B1V-C-20JI |
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PSD5XX Famly
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9.3.13 Port C and Port D – Functionality and Structure
Port C and D are identical in function and structure and each can be configured to perform
one or more of the following operating modes:
J
Standard MCU I/O Mode
J
PLD Input – direct input to ZPLD
J
Address Out – latched address outputs
– Port C: A[0-7] are asigned to pins PC[0-7]
– Port D: A[0-7] for 8-bit multiplexed bus, or A[8-15] for 16-bit multiplexed bus are
assigned to pins PD[0-7]
J
Data Port
– Port C: D[0-7] for 8-bit non-multiplexed bus
– Port D: D[8-15] for 16-bit non-multiplexed bus
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Open Drain – select CMOS or Open Drain driver
Figures 23 and 24 show the structure of a Port C or D pin. If the pin is configured as output
port, the multiplexer selects one of the two inputs as output. If the pin is configured as input,
the input connects to :
J
Data In Register as input in the Standard MCU I/O Mode
or
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ZPLD input
9.3.14 Port E – Functionality and Structure
Port E can be configured to perform one or more of the following functions:
J
Standard MCU I/O Mode
J
PLD I/O
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Address Out – latched address lines A[0-7] are assigned to pins PE[0-7].
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Special Function Out – in this mode, Port E pin is configured as an output port for the
following signals:
PE2 – INTERRUPT – interrupt output from Interrupt Controller
PE4 – Terminal Count output, Timer0
PE5 – Terminal Count output, Timer1
PE6 – Terminal Count output, Timer2
PE7 – Terminal Count output, Timer3
J
Alternate Function In – in this mode, the inputs to Port E pins are:
PE0 – BHE/ or PSEN/ or WRH/ or UDS/ or SIZ0
PE1 – ALE
PE3 – TIMER0-IN
:load/store/enable/ disable input to Timer 0
PE4 – TIMER1-IN
:load/store/enable/disable input to Timer 1
PE5 – TIMER2-IN
:load/store/enable/disable input to Timer 2
PE6 – TIMER3-IN
:load/store/enable/disable input to Timer 3
PE7 – APD CLK
:clock input for Automatic Power Down Counter
Figure 25 shows the structure of a Port E pin. The Control Logic block selects one of four
sources through the multiplexer for pin output. If the pin is configured as input, the input
goes to:
J
Data In Register as input in Standard MCU I/O Mode
or
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PE Macrocell as PLD input
or
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Alternate Function In
I/OPorts
(Cont.)
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