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| 型號(hào)： | ZPSD511B1-12LI |
| 英文描述： | Field-Programmable Peripheral |
| 中文描述： | 現(xiàn)場(chǎng)可編程外圍 |
| 文件頁(yè)數(shù)： | 91/153頁(yè) |
| 文件大小： | 1036K |
| 代理商： | ZPSD511B1-12LI |
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PSD5XX Famly
88
9.6.2.5 Software Load/Store Register:
Each bit in this register enables a load to the corresponding Counter/Timer from its
associated Image Register in Waveform, Pulse or WatchDog modes. The actual counts
are stored in their corresponding Image Register in event Counter or time capture modes.
Bit 6 of the Command Register must be set to “1” before writing to the software load/store
register.
Counter/Timer
Registers
(Cont.)
Software Load/Store 0 Bit:
If this bit is set to
1: Counter/Timer0 CNTR0 gets loaded from the Image
Register IMG0 or CNTR0 stores into IMG0 based on the
mode of operation
**
.
Software Load/Store 1 Bit:
If this bit is set to
1: Counter/Timer1 CNTR1 gets loaded from the Image
Register IMG1 or CNTR1 stores into IMG1 based on the
mode of operation
**
.
Software Load/Store 2 Bit:
If this bit is set to
1: Counter/Timer2 CNTR2 gets loaded from the Image
Register IMG2.
Software Load/Store 3 Bit:
If this bit is set to
1: Counter/Timer3 CNTR3 gets loaded from the Image
Register IMG3 or CNTR3 stores into IMG3 based on the
mode of operation
**
.
**
Load operation takes place in Waveform, Pulse and WatchDog mode.
Store operation takes place in Event Count and Time Capture mode.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
*
*
*
*
Software
Load/Store 3 Load/Store 2 Load/Store 1 Load/Store 0
Software
Software
Software
NOTE:
*
= Not used.
The Software load/store bits are automatically cleared by the served Counter.
In addition to four CTU registers, there are delay cycle and Counter/Timer status registers.
These are summarized on the following pages.
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