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| 型號： | ZPSD503B1V |
| 英文描述： | Field Programmable Microcontroller Peripherals(可編程邏輯，零功耗，16K位SRAM,40個可編程I/O,通用PLD有61個輸入) |
| 中文描述： | 現(xiàn)場可編程微控制器外圍設(shè)備（可編程邏輯，零功耗，16K的位的SRAM，40余個可編程輸入/輸出，通用PLD的有61個輸入） |
| 文件頁數(shù)： | 6/142頁 |
| 文件大?。?/td> | 786K |
| 代理商： | ZPSD503B1V |
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ZPSD5XX Famly
7-6
General
Description
(Cont.)
The peripheral PLD (PPLD) generates outputs to the Counter/Timer unit and the Interrupt
Controller. The PPLD outputs to the Counter/Timer enable, disable or trigger counting or
time capture. This unique capability enables the user to implement in the PPLD the exact
conditions for the timer to count or generate an output. The PPLD also generates four
outputs to the Interrupt Controller which enables the user to define the exact conditions for
interrupt generation.
The ZPLDs are designed to consume minimum power using Zero Power design techniques.
A configuration bit (Turbo bit), that can be set by the MCU, will automatically place the
ZPLDs into standby if no inputs are changing. Any unused product terms will be turned off
during programming and will not consume any power in the system.
The ZPSD5XX has 40 I/O pins that are divided into 5 ports. Each I/O pin can be individually
configured to provide many functions. Ports A, B and E have the capability to be
configured as standard MCU I/O ports, GPLD I/O, latched address outputs for multiplexed
address/data controllers, or special function I/O (e. g., Counter/Timer and Interrupts).
Ports C and D are standard I/O ports that can also be configured as ZPLD inputs or data
bus for microcontrollers with non-multiplexed bus.
The ZPSD5XX can easily interface with no “glue-logic” to a variety of 8 and 16-bit
microcontrollers with a multiplexed or non-multiplexed bus. All of the control signals are
connected to the three ZPLDs enabling the user to generate timing and decoding signals for
external peripherals. For controllers that do not have a Reset output, the ZPSD5XX can
generate a RESET output based on its RESET input that includes hysteresis.
The Counter/Timer unit provides four 16 bit highly flexible Counter/Timers. Each
Counter/Timer has five modes of operation: pulse, waveform, event counting, time capture
and watchdog (Real Time Clock). Counter 2 can operate as a Watch Dog Timer. Each
Counter/Timer can be programmed to count up or down. The inputs to the Counter/Timer
unit, which enable/disable counting or triggering an operation, can originate from the PPLD
or directly from the pins. The maximum operating frequency of each counter is 7.5 MHz.
The input clock can be divided (up to 280) before driving the Counter/Timer unit using the 4
to 280 range prescaler .
The ZPSD5XX includes an 8 level priority encoded Interrupt Controller. The Interrupt
Controller accepts 4 user defined interrupts and 4 Terminal Counts from the Counter/Timer.
Each interrupt can be individually masked and configured to be level or edge sensitive. A 3
bit interrupt vector is generated that can be read by the microcontroller. The serviced
interrupt will be cleared automatically after the microcontroller has read the interrupt vector.
The ZPSD5XX contains EPROM and scratchpad SRAM. The EPROM densities are 256K,
512K bit and 1M bit and are divided into four blocks. Each block can be located in a
different address location. The access time of the EPROM includes the address latching
and DPLD decoding. The 16 Kbit Standby SRAM may be used as an extension of the
microcontroller SRAM and also to store backup information that is necessary after a system
power down or power failure. Power to the SRAM is supplied by the Vstby pin. Switching
between V
CC
and Vstby occurs automatically when V
CC
power is removed.
A four bit Page Register enables microcontrollers with limited address space easy access
to the I/O Section, EPROM and SRAM . The Page Register outputs are connected to all
ZPLDs and can be used to page external devices as well as the internal ZPSD5XX
functional units.
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